USB3500 芯片手册

USB3500

PRODUCT FEATURES

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UTMI+ Specification, Revision 1.0.

On-The-Go Supplement Revision 1.0a specification.

Functional as a host, device or OTG PHY

.

UTMI+ Level 3

Supports HS SOF and LS keep alive pulse.

Supports Host Negotiation Protocol (HNP) and

Session Request protocol (SRP

.)

Integrated 24MHz Crystal Oscillator supports either

crystal operation or 24MHz external clock input.

后面由

CLKOUT

输出

60MHz

时钟

Internal PLL for 480MHz Hi-Speed USB operation.

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Chapter 1 General Description

The USB3500 uses a UTMI+ interface to connect to an SOC or FPGA or custom ASIC.

SOC/FPGA/ASIC

Including Device Controller

USB3500

V

BUS

Hi- Speed

USB App.

UTMI+

Link

UTMI+

Interface

UTMI+

Digital

Logic

USB 2.0

Analog

w/ OTG

ID

DM

DP

USB

Connector

(

Standard

or Mini)

Figure 1.1 Basic UTMI+ USB Device Block Diagram

AD

DE

D

FE

AT

UR

ES

UTMI+ Level 3

USB2.0 Peripheral, host controllers, On-the-

Go devices

(HS, FS, LS, preamble packet)

UTMI+ Level 2

USB2.0 Peripheral, host controllers, Onthe-

Go devices

(HS, FS, and LS but no preamble packet)

UTMI+ Level 1

USB2.0 Peripheral, host controllers, and

On- the-Go devices

(HS and FS Only)

USB3500

UTMI+ Level 0 USB2.0

Peripherals Only

Figure 1.2 UTMI+ Level 3 Support

Chapter 2 Functional Overview

Chapter 3

引脚定义

Pin Definitions

Table 3.1 USB3500 Pin Definitions

DIRECTION,

TYPE

Input

ACTIVE

LEVEL

N/A

PIN

1

NAME

XCVRSEL[1:0]

DESCRIPTION

Transceiver Select.

These signals select between the

FS and HS transceivers:

Transceiver select.

00: HS

01: FS

10: LS

11: LS data, FS rise/fall times

Termination

Select

.

This

signal

selects

between

the

FS and HS terminations:

0: HS termination enabled

1: FS termination enabled

2

TERMSEL

Input

N/A

3

TXREADY

Output

High

Transmit Data Ready.

If TXVALID is asserted, the Link

must always have data available for clocking into the TX

Holding Register on the rising edge of CLKOUT.

TXREADY is an acknowledgement to the Link that the

transceiver has clocked the data from the bus and is

ready for the next transfer on the bus.

If TXVALID is

negated, TXREADY can be ignored by the Link.

4

VBUS

I/O,

Analog

Input,

Analog

Input

N/A

VBUS pin of the

USB cable.

5

ID

N/A

ID pin of the

USB cable.

6

SUSPENDN

Low

Suspend. Places the transceiver in a mode that draws

minimal power from supplies. In host mode, R

PU

is

removed during suspend. In device mode, R

PD

is

controlled by TERMSEL. In suspend mode the clocks

are off.

0: PHY in suspend mode

1: PHY in normal operation

Transmit Valid.

Indicates that the DATA bus is valid for

transmit. The assertion of TXVALID initiates the

transmission of SYNC on the USB bus. The negation

of TXVALID initiates EOP on the USB.

Control inputs (OPMODE[1:0],

TERMSEL,XCVERSEL)

must

not

be

changed

on

the

de- assertion or assertion of TXVALID.

7

TXVALID

Input

High

8

RESET

Input

High

Reset. Reset all state machines.

After coming out of

reset, must wait 5 rising edges of clock before

asserting TXValid for transmit.

Assertion of Reset: May be asynchronous to

CLKOUT

De- assertion of Reset: Must be synchronous to

CLKOUT

D+ pin of the

USB cable.

9

DP

I/O,

Analog

N/A

10

DM

I/O,

Analog

Input

N/A

D- pin of the

USB cable.

11

CHRGVBUS

High

Charge VBUS through a resistor to VDD3.3.

0: do not charge VBUS

1: charge VBUS

Receive

Active.

Indicates

that

the

receive

state

machine has detected Start of Packet and is active.

Operational Mode. These signals select between

the various operational modes:

12

RXACTIVE

Output

High

13

OPMODE[1]

Input

N/A

Input

N/A

[1] [0] Description

0 0 0: Normal Operation

0 1 1: Non-driving (all terminations removed)

1 0 2: Disable bit stuffing and NRZI encoding

1 1 3: Reserved

ID Digital.

Indicates the state of the ID pin.

0: connected plug is a mini-A

1: connected plug is a mini-B

ID Pull-up. Enables sampling of the analog ID line.

Disabling the ID line sampler will reduce PHY power

consumpti on.

（

chapter 4.7.1

）

0: Disable sampling of ID line.

1: Enable sampling of ID line.

60MHz reference clock output.

All UTMI+ signals are

driven synchronous to this clock.

Line State.

These signals reflect the current state of

the

USB

data

bus

in

FS

mode.

Bit

[0]

reflects

the

state of DP and bit [1] reflects the state of DM. When

the

device

is

suspended

or

resuming

from

a

suspended

state,

the

signals

are

combinatorial.

Otherwise, the signals are synchronized to CLKOUT

.

[1] [0] Description

0 0 0: SEO

0

1 1: J State

1

0 2: K State

1 1 3: SE1

The LineStatesignals are used by the SIE for

detecting reset, speed signaling, packet timing,

and to transition from one behavior to another

14

ID_DIG

Output

High

15

IDPULLUP

Input

High

16

CLKOUT

Output,

CMOS

Output

Output

N/A

17

LINESTATE[1:0]

N/A

N/A

18

HOSTDISC

Output

High

Host Disconnect

. In HS Host mode this indicates to

that a downstream device has been disconnected.

Automatically reset to 0b when Low Power Mode is

entered.

Discharge VBUS through a resistor to ground.

0: do not discharge VBUS

1: discharge VBUS

Session End. Indicates that the voltage on Vbus is

below its

B-Device Session End threshold.

0: VBUS > V

SessEnd

1: VBUS < V

SessEnd

8-bit bi-directional data bus. Data[7] is the MSB and

Data[0] is the LSB.

19

DISCHRGVBUS

Input

High

20

SESSEND

详见

4.7.2

Output

High

21

DATA[7:0]

I/O,

CMOS,

Pull-low

Output

N/A

22

RXVALID

High

Receive Data Valid.

Indicates that the DATA bus has

received

valid

data.

The

Receive

Data

Holding

Register is full and ready to be unloaded.

The Link

is

expected

to

register

the

DATA

bus

on

the

next

rising edge of CLKOUT

.

23

SESSVLD

详见

4.7.2

Output

High

Session

Valid.

Indicates

that

the

voltage

on

Vbus

is

above the indicated threshold.

0: VBUS < V

SessVld

1: VBUS > V

SessVld

24

DPPD

Input

N/A

DP Pull-down Select. This signal enables the 15k

Ohm pull- down resistor on the DP line.

0: Pull- down resistor not connected to DP

1: Pull-down resistor connected to DP

DM Pull-down Select. This signal enables the 15k

Ohm pull-down resistor on the DM line.

0: Pull-down resistor not connected to DM

1: Pull-down resistor connected to DM

Receive Error. This output is clocked with the same

timing

as

the

receive

DATA

lines

and

can

occur

at

anytime during a transfer.

0: Indicates no error.

1: Indicates a receive error has been detected.

VBUS Valid. Indicates that the voltage on Vbus is

above the indicated threshold.

0: VBUS < V

VbusVld

1: VBUS > V

VbusVld

25

DMPD

Input

N/A

26

RXERROR

Output

High

27

VBUSVLD

详见

4.7.2

Output

High

Chapter 4

发送数据、接收数据的时序图。

4.1

8bit Bi-Directional Data Bus Operation

The USB3500 supports an 8-bit bi-directional parallel interface.

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CLKOUT runs at 60MHz

USB2.0

最高

480 Mbs=60MHz*8bit

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The 8-bit data bus (DATA[7:0]) is used for

transmit when TXVALID = 1

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The 8-bit data bus (DATA[7:0]) is used for

receive when TXVALID = 0

Figure 6.1

shows the relationship between CLKOUT and the transmit data transfer signals in

FS mode.

TXREADY is only asserted for one CLKOUT per byte time to signal the Link that the data on the DATA

lines has been read by the PHY

. The Link may hold the data on the DATA lines for the duration of the

byte time. Transitions of TXVALID must meet the defined setup and hold times relative to CLKOUT

.

Figure 6.1 FS CLK

Relationship to Transmit Data and Control Signals

Figure 6.2

shows the relationship between CLKOUT and the receive data control signals in FS mode.

RXACTIVE

“frames”

a

packet,

transitioning

only

at

the

beginning

and

end

of

a

packet.

However

transitions

of

RXVALID

may

take

place

any

time

8

bits

of data

are

available.

Figure

6.2

also shows

how

RXVALID

is

only

asserted

for

one

CLKOUT

cycle

per

byte

time

even

though

the

data

may

be

presented

for

the

full

byte

time.

The

XCVRSELECT

signal determines

whether

the

HS or

FS

timing

relationship is applied to the data and control signals.

Figure 6.2 FS CLK Relationship to

Receive Data and Control Signals

4.2TX Logic (send data to

USB cable

)

接收总线上的并行数据并进行相应的转换

.

Upon

valid

assertion

of

the

proper

TX

control

lines

by

the

Link and TX State Machine, the TX LOGIC block will synchronously shift, at either the FS or HS rate,

the data to the FS/HS TX block to be transmitted on the USB cable.

Figure 6.3 Transmit Timing for a Data Packet

PID

也是数据中的一 部分，一个字节。

Sync

在

TXVA LID

之后两个时钟上升沿。

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The

Link asserts TXVALID to begin a transmission.

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当

TXREAD=1 TXDATA

开始发数据

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The Link must assume that the USB3500 has consumed a data byte if TXREADY and TXVALID are

asserted

on the rising edge of CLKOUT.

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PID

coincident with the assertion of TXVALID.

一起出现

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TXREADY is sampled by the Link on the rising edge of CLKOUT

.

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The Link

negates TXVALID to complete a packet.

Once negated, the transmit logi c(ready

信号是芯片

产生的

) will never reassert TXREADY until after the EOP has been generated.

(TXREADY will not

re-assert until TXVALD asserts again

.) TXREADY=0

两个时钟沿后，

EOP

发送结束。

the minimum inter-packet delays identified in the USB 2.0 specification.

过一段时间之后才能再次发

送数据，时间如何确定？

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The USB3500 is ready to transmit another packet immediately. However,

the Link must conform to

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Supports high speed disconnect detect through the HOSTDISC pin. In Host mode the USB3500 will

sample the disconnect comparator at the 32nd bit of the 40 bit long

EOP during SOF packets.

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Supports FS pre-amble for FS hubs with a LS device.

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Supports LS keep alive by receiving the SOF PID.

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Supports Host mode resume K which ends

with two low speed times of SE0 followed by 1 FS “J”.

4.3

RX Logic

Upon valid assertion of the proper RX control lines, the RX Logic block will provide bytes to the DATA

bus.

Figure 6.4 Receive Timing for Data with Unstuffed Bits

USB

线开始传输数据时

RXACTIVE