Vivado下创建基于AXI

以参考我之前的文章，用

HLS

做，比本文的方 法简单快捷。

`timescale 1 ns / 1 ps

// User parameters ends

module myip_v1_0_S00_AXI #

(

// Users to add parameters here

// Do not modify the parameters beyond this line

)

(

// Width of S_AXI data bus

parameter integer C_S_AXI_DATA_WIDTH

= 32,

// Width of S_AXI address bus

parameter integer C_S_AXI_ADDR_WIDTH

= 4

// Users to add ports here

output wire pwm_out,

// Global Clock Signal

input wire

S_AXI_ACLK,

// Global Reset Signal. This Signal is Active LOW

input wire

S_AXI_ARESETN,

// Write address (issued by master, acceped by

// User ports ends

// Do not modify the ports beyond this line

Slave)

input wire [C_S_AXI_ADDR_WIDTH-1 : 0]

S_AXI_AWADDR,

// Write channel Protection type. This signal indicates

the

// privilege and security level of the transaction,

and whether

access.

input wire [2 : 0] S_AXI_AWPROT,

// Write address valid. This signal indicates that the

// the transaction is a data access or an instruction

master signaling

// valid write address and control information.

input wire

S_AXI_AWVALID,

// Write address ready. This signal indicates that the

slave is ready

signals.

output wire

S_AXI_AWREADY,

// Write data (issued by master, acceped by Slave)

input wire [C_S_AXI_DATA_WIDTH-1 : 0]

// to accept an address and associated control

S_AXI_WDATA,

// Write strobes. This signal indicates which byte

lanes hold

eight

// valid data. There is one write strobe bit for each

// bits of the write data bus.

input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0]

S_AXI_WSTRB,

// Write valid. This signal indicates that valid write

// data and strobes are available.

input wire

S_AXI_WVALID,

// Write ready. This signal indicates that the slave

// can accept the write data.

output wire

S_AXI_WREADY,

// Write response. This signal indicates the status

// of the write transaction.

output wire [1 : 0] S_AXI_BRESP,

// Write response valid. This signal indicates that the

channel

// is signaling a valid write response.

output wire

S_AXI_BVALID,

// Response ready. This signal indicates that the

master

// can accept a write response.

input wire

S_AXI_BREADY,

// Read address (issued by master, acceped by

Slave)

input wire [C_S_AXI_ADDR_WIDTH-1 : 0]

S_AXI_ARADDR,

// Protection type. This signal indicates the privilege

// and security level of the transaction, and

whether the

access.

input wire [2 : 0] S_AXI_ARPROT,

// Read address valid. This signal indicates that the

// transaction is a data access or an instruction

channel

// is signaling valid read address and control

information.

input wire

S_AXI_ARVALID,

// Read address ready. This signal indicates that the

slave is

// ready to accept an address and associated

control signals.

output wire

S_AXI_ARREADY,

// Read data (issued by slave)

output wire [C_S_AXI_DATA_WIDTH-1 : 0]

S_AXI_RDATA,

// Read response. This signal indicates the status of

the

// read transfer.

output wire [1 : 0] S_AXI_RRESP,

// Read valid. This signal indicates that the channel is

// signaling the required read data.

output wire

S_AXI_RVALID,

// Read ready. This signal indicates that the master

can

// AXI4LITE signals

reg [C_S_AXI_ADDR_WIDTH-1 : 0]

axi_awaddr;

reg

axi_awready;

reg

axi_wready;

reg [1 : 0]

axi_bresp;

reg

axi_bvalid;

reg [C_S_AXI_ADDR_WIDTH-1 : 0]

axi_araddr;

reg

axi_arready;

reg [C_S_AXI_DATA_WIDTH-1 : 0]

axi_rdata;

reg [1 : 0]

axi_rresp;

);

// accept the read data and response information.

input wire

S_AXI_RREADY

reg

axi_rvalid;

//------------------ add by cuter---------------

wire

ovpprd;

wire

pwm_out_tmp;

reg

[C_S_AXI_DATA_WIDTH-1:0]

pwm_cnt;

//-----------------------end------------- -------

// Example-specific design signals

// local parameter for addressing 32 bit / 64 bit

C_S_AXI_DATA_WIDTH

// ADDR_LSB is used for addressing 32/64 bit

registers/memories

// ADDR_LSB = 2 for 32 bits (n downto 2)

// ADDR_LSB = 3 for 64 bits (n downto 3)

localparam integer ADDR_LSB =

(C_S_AXI_DATA_WIDTH/32) + 1;

localparam integer OPT_MEM_ADDR_BITS = 1;

//-------------- --------------------------------

//-- Signals for user logic register space example

//----------------------------------------- -------

//-- Number of Slave Registers 4

reg [C_S_AXI_DATA_WIDTH-1:0]

slv_reg0;

// used as period register

reg [C_S_AXI_DATA_WIDTH-1:0]

slv_reg1;

// used as duty register

assign S_AXI_AWREADY = axi_awready;

assign S_AXI_WREADY

= axi_wready;

assign S_AXI_BRESP

= axi_bresp;

assign S_AXI_BVALID

= axi_bvalid;

assign S_AXI_ARREADY

= axi_arready;

assign S_AXI_RDATA

= axi_rdata;

assign S_AXI_RRESP

= axi_rresp;

assign S_AXI_RVALID

= axi_rvalid;

// Implement axi_awready generation

// I/O Connections assignments

reg [C_S_AXI_DATA_WIDTH-1:0]

slv_reg2;

reg [C_S_AXI_DATA_WIDTH-1:0]

slv_reg3;

wire

slv_reg_rden;

wire

slv_reg_wren;

reg [C_S_AXI_DATA_WIDTH-1:0]

reg_data_out;

integer

byte_index;

// axi_awready is asserted for one S_AXI_ACLK clock

cycle when both

// S_AXI_AWVALID and S_AXI_WVALID are asserted.

axi_awready is

always @( posedge S_AXI_ACLK )

begin

if ( S_AXI_ARESETN == 1'b0 )

begin

axi_awready <= 1'b0;

end

else

begin

if (~axi_awready && S_AXI_AWVALID

// de-asserted when reset is low.

&& S_AXI_WVALID)

begin

// slave is ready to accept write address

when

// there is a valid write address and write

data

// on the write address and data bus. This

design

always @( posedge S_AXI_ACLK )

begin

if ( S_AXI_ARESETN == 1'b0 )

begin

axi_awaddr <= 0;

end

else

// Implement axi_awaddr latching

// This process is used to latch the address when both

// S_AXI_AWVALID and S_AXI_WVALID are valid.

// expects no outstanding transactions.

axi_awready <= 1'b1;

end

else

begin

axi_awready <= 1'b0;

end

end

end

begin

if (~axi_awready && S_AXI_AWVALID

&& S_AXI_WVALID)

// Implement axi_wready generation

// axi_wready is asserted for one S_AXI_ACLK clock

begin

// Write Address latching

axi_awaddr <= S_AXI_AWADDR;

end

end

end

cycle when both

// S_AXI_AWVALID and S_AXI_WVALID are asserted.

axi_wready is

always @( posedge S_AXI_ACLK )

begin

if ( S_AXI_ARESETN == 1'b0 )

begin

axi_wready <= 1'b0;

// de-asserted when reset is low.

end

else

begin

if (~axi_wready && S_AXI_WVALID

&& S_AXI_AWVALID)

begin

// slave is ready to accept write data when

// there is a valid write address and write

data

// on the write address and data bus. This

design

// Implement memory mapped register select and write

// expects no outstanding transactions.

axi_wready <= 1'b1;

end

else

begin

axi_wready <= 1'b0;

end

end

end