VCS 仿真指南

如果设置中使用到了

PLI

< br>就会创建

.

具体如何使用

Vi rSim

做交互调试这里也不具体介绍

,

可以参考

VirSim

的

userg uide

和

vcs

安装下面的

doc

的

tutorial.

3. VirSim

的后处理调试模式

注意 什么时候用后处理调试模式

,

什么时候使用交换模式那

?

在初步仿真的过程使用交

< br>互模式

,

若是调试一个成熟的设计或者很多人一起做调试 这样子可以使用

post-processing mode.

其主要的

方法是通过仿真运行

dump

数据在

vcd

或者

vpd

文件中

,

运行结束后通过

v cd

或者

vpd

观察运行过程的情况< /p>

,

交互调试能力相对较差

,

但是通过记录的数据可以观察出其中异常的地方

;

也 就是包括两个步骤

Write VCD+

file,View result.

>vcs source.v

–

line

–

R -PP +vcsd

其中

-R

自动运行并且生成

vcd+

-PP

编译的时候是

faster VirSim post_processing

>vcs

–

RPP source.v +vpdfile+

注意

:VirSim

只能处理

< br>VCD+

文件可以被转换成

VCD+

< br>格式的文件

.

VCD+

和

VCD

有什么不一样那

?

< br>更快

,

更小

.

VCD+

系统任务可以在

testbench

中使用也可以在仿真的时候添加

.(

注意使用到 这些系统函数时

,

在

vcs

的时候一定要添加

-I

或者

-RI.)

$$vcdpluson(level_nu mber,module_instance,….|net_or reg,….)

level_numbers

指定记录的层次

0-

记录整个指定

module_instance

的所 有信号

1-

记录指定

module_instance

顶层信号

n-

记录从顶层开始到下面的

n

层例化模块的信号

module_instance

指定例化名

net_ or reg

指定特定的

wire

或者

reg

作为记录的对象

,

默 认是所有信号

.

$$vcdplusoff(module_instance,….|net_ or reg,…)

其他系统函数可以参见

VCS quick reference.

二

.

其他情况

注意区别的两个方面

:

1.

–

R

–

I

不同于

-RI

-R

–

I

是 编译成

VirSim

的可执行文件而且马上运行仿真

是编译成

VirSim

的可执行文件并且调用

VirSim.

2.

–

R

–

PP

不同于

-RPP

-R

–

PP

是编译成

VirSim

的可执行文件并且在运行的时候加快输出

VCD+

文件

-RPP

是在存在

VCD+

的条件下 调用

VirSim

进行

post processing

的调试

.

门级 仿真需要反标

SDF

文件

,

testbench

中添加

$$sdf_annotate

系统函数

.

并且在编译的时候注意要使

用

standcell< /p>

的仿真库

.

Compile-Time Options

********************

-f

Specifies a file that contains a list of pathnames to source files

and compile-time options.

-F

Same as the -f option but allows you to specify a path to the file

and the source files listed in the file do not have to be absolute

pathnames.

-h

Displays a succinct description of the most commonly used compile-time

and runtime options.

-l

(lower case L) Specifies a log file where VCS records compilation

messages and runtime messages if you include the -R, -RI, or

-RIG options.

-line

Enables stepping through the code and source line breakpoints in VirSim.

-M

Enables incremental compilation, but do not overwrite the makefile.

-Mupdate

Enable incremental compilation and overwrite the make file.

-notice

Enables verbose diagnostic messages.

-o

Specifies the name of the executable file that is the product of

compilation. The default name is simv ( on Windows).

-ova_cov

Enables functional coverage.

-P <>

Specifies a PLI table file.

-R

Run the executable file immediately after VCS links together the

executable file. You can add any runtime option to the vcs command

line.

-s

Stop simulation just as it begins. Use this option with the -R and

+cli options.

-timescale=/

If only some source files contain the `timescale compiler directive

and the ones that don't appear first on the vcs command line, use

this option to specify the time scale for these source files.

-V

Enables the verbose mode.

-v

Specifies a Verilog library file to search for module definitions.

-vera

Specifies the standard VERA PLI table file and object library.

-y

Specifies a Verilog library directory to search for module

definitions.

+2state

Enables 2 state simulation.

+cli+[=]1|2|3|4

Enable CLI debugging.

1 enables you to see the values of nets and registers and deposit

values to registers.

2 also enables breakpoints on value changes of nets and registers.

3 also enables you to force a value on nets.

4 also enables you to force a value on a register.

You can specify a module to enable CLI debugging only for instances

of the module.

+define+=

Defines a text macro. Test for this definition in your Verilog

source code using the `ifdef compiler directive.

+incdir+

Specifies the directories that contain the files you specified with

the `include compiler directive. You can specify more that one

directory, separating each path name with the + character.

+libext+

Specifies that VCS only search the source files in a Verilog library

directory with the specified extension. You can specify more than one

extension, separating each extension with the + character.

For example, +libext++.v specifies searches library files with no

extension and library files with the .v extension.

Enter this option when you enter the -y option.

+maxdelays

Use maximum value when min:typ:max values are encountered in delay

specifications SDF files.

+mindelays

Use minimum value when min:typ:max values are encountered in delay

specifications and SDF files.

+notimingcheck

Suppresses timing checks in specify blocks.

+plusarg_ignore

Also enter this option in the file that you specify with the -f option

so that VCS does not pass to the simv executable or to VirSim the

options that follow in the file. Use this option with the

+plusarg_save option to specify that other options should

not be passed.

+race

Specifies that VCS generate a report, during simulation, of all the

race conditions in the design and write this report in the

file.

+race=all

Analyzes the source code during compilation to look for coding

styles that cause race conditions.

+rad or +rad+2

Performs aggressive optimizations on your design.

+rad+1 or +radlite or +radlight

Performs less aggressive optimizations on your design.

+v2k

Enables the use of new Verilog constricts in the 1364-2001 standard.

Runtime Options

***************

-i

Specifies a file containing CLI commands that VCS executes when

simulation starts.

-l

Specifies writing all messages from simulation to the specified

file as well as displaying these messages in the standard output.

This option begins with the letter

-ova_cov

Enables functional coverage reporting.

-s

Stops simulation just as it beings, and enters interactive mode.

Use with the +cli+ option.

-V

Verbose mode. Print VCS version and extended summary information.

Prints VCS compile and run-time version numbers, and copyright

information, at start of simulation.

-vcd

Sets the output VCD file name to the specified file.

The default filename is .

A $$dumpfile system task in the Verilog source code will override

this option.

+maxdelays

Species using the compiled SDF file for maximum delays generated

by the +allmtm compile-time option.

Also specifies using maximum delays for SWIFT VMC or SmartModels

or Synopsys hardware models if you also enter the

+override_model_delays runtime option.

+mindelays

Specifies using the compiled SDF file for minimum delays generated

by the +allmtm compile-time option.

Also specifies using minimum delays for SWIFT VMC or SmartModels

or Synopsys hardware models if you also enter the

+override_model_delays runtime option.

+notimingcheck

Suppress timing checks.

+override_model_delays

Enables you to use the +mindelays, +typdelays, or +maxdelays runtime

options to specify timing for SWIFT SmartModels or Synopsys hardware

models.

+sdfverbose