芯片英文简介

74LS161

Datasheet

General Description

These synchronous, preset table counters feature an internal carry look-ahead for

application in high-speed counting designs. The DM74LS161A are 4-bit binary

counters. The carry output is decoded by means of a NOR gate, thus preventing spikes

during the normal counting mode of operation. Synchronous operation is provided by

having all flip-flops clocked simultaneously so that the outputs change coincident

with each other when so instructed by the count-enable inputs and internal gating.

This mode of operation eliminates the output counting spikes which are normally

associated with asynchronous (ripple clock) counters. A buffered clock input triggers

the four flip-flops on the rising (positive-going) edge of the clock input waveform.

These counters are fully programmable; that is, the outputs may be preset to either

level. As presetting is synchronous, setting up a low level at the load input disables

the counter and causes the outputs to agree with the setup data after the next clock

pulse, regardless of the levels of the enable input. The clear function for the

DM74LS161A is asynchronous; and a low level at the clear input sets all four of the

flip-flop outputs LOW, regardless of the levels of clock, load, or enable inputs.

(

这些同 步

,

预置表计数器为应用在高速计数功能内部携带有预见性的设 计。

DM74LS161A

4

比特二 进制计数器。套利或非门的输出是通过解码

,

从而防止在正

常峰值计数的操作模式。同步操作是由所有人字拖时钟同步

,

以便输出变化互相

重合时

,

< br>指示

count-enable

输入和内部控制。

这种模式的操作消除了输出计数峰

值通常与异步计数器

(

波纹时钟

)

。

一个缓冲时钟输入触发四人字拖

(

正向的

边缘

的时钟输入波形上升。

这些计数器是完全可编程

;

也就是说

,

输出可以被预设的水

平。

作为预设 定是同步的

,

建立一个低水平的负载输入禁用计数器