W25Q128主要操作时序图

7.2.5 Write Enable (06h)

The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to

a 1. The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block

Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction. The Write

Enable instruction is entered by driving /CS low, shifting the instruction code “06h” into the Data Input

(DI) pin on the rising edge of CLK, and then driving /CS high.

Figure 4. Write Enable Instruction Sequence Diagram

7.2.7 Write Disable (04h)

The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register

to a 0. The Write Disable instruction is entered by driving /CS low, shifting the

instruction code “04h”

into the DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up

and

upon

completion

of

the

Write

Status

Register,

Erase/Program

Security

Registers,

Page

Program,

Quad Page Program, Sector Erase, Block Erase and Chip Erase instructions.

Write Disable instruction can also be used to invalidate the Write Enable for V

olatile Status Register

instruction.

Figure 6. Write Disable Instruction Sequence Diagram

7.2.8 Read Status Register-1 (05h) and Read Status Register-2 (35h)

The

Read

Status

Register

instructions

allow

the

8-bit

Status

Registers

to

be

read.

The

instruction

is

entered by driving /CS low and shifting the instruction code “05h” for Status Register

-

1 or “35h” for

Status Register-2 into the DI pin on the rising edge of CLK. The status register bits are then shifted out

on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 7.

The Status Register bits are shown in Figure 3a and 3b and include the

BUSY

, WEL, BP2-BP0, TB,

SEC,

SRP0,

SRP1,

QE,

LB[3:1],

CMP

and

SUS

bits

(see

Status

Register

section

earlier

in

this

datasheet).

The Read Status Register instruction may be used at any time, even while a Program, Erase or Write

Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when

thecycle is complete and if the device can accept another instruction. The Status Register can be read

continuously, as shown in Figure 7. The instruction is completed by driving /CS high.

Figure 7. Read Status Register Instruction Sequence Diagram

//BIT7

6

5

4

3

2

1

0

//SPR

RVTB BP2 BP1 BP0 WEL BUSY

//SPR:

默认

0,

状态寄存器保护位

,

配合

WP

使用

/ /TB,BP2,BP1,BP0:FLASH

区域写保护设置

//WEL:

写使能锁定

忙标记位

(1,

< br>忙

;0,

空闲

)

//

默认

:0x00

7.2.10 Read Data (03h)

The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The

instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed

by a 24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the rising edge

of the CLK pin. After the address is received, the data byte of the addressed memory location will be

shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address

is automatically incremented to the next higher address after each byte of data is shifted out allowing

for

a

continuous

stream

of

data.

This

means

that

the

entire

memory

can

be

accessed

with

a

single

instruction as long as the clock continues. The instruction is completed by driving /CS high.

The Read Data instruction sequence is shown in Figure 9. If a Read Data instruction is issued while an

Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any

effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of

f

R

(see AC Electrical Characteristics)

Figure 9. Read Data Instruction Sequence Diagram

7.2.21 Page Program (02h)

The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at

previously

erased

(FFh)

memory

locations.

A

Write

Enable

instruction

must

be

executed

before

the

device

will

accept

the

Page

Program

Instruction

(Status

Register

bit

WEL=

1).

The

instruction

is

in

itiated

by

driving

the

/CS

pin

low

then

shifting

the

instruction

code

“02h”

followed

by

a

24

-bit

address

(A23-A0)

and

at

least

one

data byte,

into

the

DI

pin.

The

/CS

pin

must

be

held

low

for

the

entire

length

of

the

instructionwhile

data

is

being

sent

to

the

device.

The

Page

Program

instruction

sequence is shown in Figure 19.

If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits)

should be set to 0. If the last address byte is not zero, and the number of clocks exceed the remaining

page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes

(a

partial page) can be programmed without having any effect on other bytes within the same page. One

condition to perform a partial page program is that the number of clocks can not exceed the remaining

page length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of

the page and overwrite previously sent data.

As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last

byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS is

driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC

Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may

still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program

cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions

again.

After

the

Page

Program

cycle

has

finished

the

Write

Enable

Latch

(WEL)

bit

in

the

Status

Register

is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by

the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits.

Figure 19. Page Program Instruction Sequence Diagram

7.2.23 Sector Erase (20h)

The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of

all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase

Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin

low and shift

ing the instruction code “20h” followed a 24

-bit sector address (A23-A0) (see Figure 2).

The Sector Erase instruction sequence is shown in Figure 21.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done