-
JEDEC
STANDARD
Stress-Test-Driven
Qualification of
Integrated
Circuits
IC
集成电路压力测试考核
JESD47I
(
R
evision of JESD47H.01, April 2011)
JULY 2012
JEDEC SOLID STATE TECHNOLOGY
ASSOCIATION
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JEDEC Standard
No. 47I
Page 5
5.5
Device qualification requirements
(cont’d)
STRESS DRIVEN
QUALIFICATION OF INTEGRATED CIRCUITS
IC
集成电路压力测试考核
(From JEDEC
Board Ballot, JCB-12-24, formulated under the
cognizance of the JC14.3 Subcommittee on
Silicon Devices Reliability
Qualification and Monitoring.)
通过
JEDEC
委员会
JCB-12-24
号投票，在
JC14.3
硅晶圆器件可靠性考核和监控小组委员会审理后
系统地阐述和制定
1
Scope
范围
This standard describes a baseline set
of acceptance tests for use in qualifying
electronic components as
new products,
a product family, or as products in a process
which is being changed.
这个文档描述了用于考核新产品、同族器件或工艺变更的可接受的基准测试标准
These tests are capable of
stimulating and precipitating semiconductor device
and packaging failures. The
objective
is to precipitate failures in an accelerated
manner compared to use conditions. Failure Rate
projections usually require larger
sample sizes than are called out in qualification
testing. For guidance
on projecting
failure rates, refer to JESD85 Methods for
Calculating Failure Rates in Units of FITs. This
qualification standard is aimed at a
generic qualification for a range of use
conditions, but is not
applicable
at
extreme use conditions such as military
applications, automotive under-the-hood
applications, or uncontrolled avionics
environments, nor does it address
2
nd
level reliability
considerations,
which are addressed in
JEP150. Where specific use conditions are
established, qualification testing
tailored to meet those specific
requirements can be developed, using JESD94 that
will result in a better
optimization of
resources.
这些测试
用于加速和诱发半导体器件和封装的失效。目的是通过比使用环境相比加速的方式来促
成
失效。相比考核测试，失效率的预测需要更多的样品数量。如果需要计算预期的失效率，请参
考
JESD85 Methods for Calculating
Failure Rates in Units of FITs
。本考核标准用于制
定一系列适用于
一般使用环境下的通用考核标准，而不是用于例如军工应用，汽车电子，
或者不受控的航天电子
等极端使用环境；同时本标准也不解决
J
EP150
标准中提出的
2nd
等级可
靠性问题。在确定具体使
用条件的情况下，可以使用
JESD9
4
开发适合于满足这些特定要求的考核测试，从而更好地优化测
试资源。
This set of tests
should not be used indiscriminately. Each
qualification project should be examined for:
a)
Any potential new and
unique failure mechanisms.
b)
Any situations
where these tests/conditions may induce invalid or
overstress failures.
注意：不要不加选择地使用本文档中的测试。
应对每个考核项目进行确认：
a
）是否存在任何潜在的新的和独特的失效机制。
< br>b
）任何测试或使用条件可能导致的失效或过应力失效情况。
JEDEC Standard No. 47I
Page 6
5.5
Device qualification requirements
(cont’d)
If it is known or suspected that
failures either are due to new mechanisms or are
uniquely induced by the
severity of the
test conditions, then the application of the test
condition as stated is not recommended.
Alternatively, new mechanisms or
uniquely problematic stress levels should be
addressed by building an
understanding
of the mechanism and its behavior with respect to
accelerated stress conditions (Ref.
JESD91, “Method for Developing
Acceleration Models for Electronic Component
Failure Mechanisms”
and JESD94,
“Application Specific Qualification using
Knowledge Based Test Methodology”).
Consideration
of PC board assembly-level effects may also be
necessary. For guidance on this, refer to
JEP150, Stress-Test-Driven
Qualification of and Failure Mechanisms Associated
with Assembled Solid
State Surface-
Mount Components
.
This document
does not relieve the supplier of the
responsibility to assure that a product meets the
complete set of its requirements.
如果已知或怀疑失效是由于新机制
或者独特的严苛测试条件引起，则不建议使用本文档描述的测
试条件。
< br>
作为一种选择，可以通过理解器件在加速应力条件下的失效机制和表现，来解决
新的失
效机制或独特的失效问题（参考
JESD91
，
“
电子元器件失效机制加速模型的研究方法
”
和
JESD94
，
“
基于测试方法学的特殊考核
“
）
。
必须需要考虑
PCB
板级封装的影响。
有关这方面的指导，请参阅
JEP150<
/p>
，与
SMT
贴装元件相关
的压力测试考核和失效机制。
本文件并不免除供应商确保产品符合其全部要求的责任。
2
Reference documents
参考文件
The revision of the
referenced documents shall be that which is in
effect on the date of the qualification
plan.
2.1 Military
军工级
MIL-STD-883,
Test Methods
and Procedures for Microelectronics
MIL-PRF 38535
2.2 Industrial
工业级
UL94,
Tests
for Flammability of Plastic Materials
for Parts in Devices and Appliances.
ASTM D2863,
Flammability of Plastic Using the
Oxygen Index Method.
IEC Publication 695,
Fire
Hazard Testing.
JEDEC Standard No. 47I
Page 7
5.5
Device qualification requirements
(cont’d)
J-STD-020, Joint IPC/JEDEC Standard,
Moisture/Reflow Sensitivity
Classification for Nonhermetic Solid
State Surface-Mount Devices
.
JP-001,
Foundry
Process Qualification Guidelines (Wafer
Fabrication Manufacturing Sites).
JESD22 Series,
Reliability Test Methods for Packaged
Devices
JESD46,
Guidelines
for
User Notification of Product/process Changes by
Semiconductor Suppliers.
JESD69,
Information
Requirements for the Qualification of Silicon
Devices
.
JESD74,
Early Life Failure Rate Calculation
Procedure for Electronic Components
.
JESD78,
IC
Latch-Up Test
.
JESD85,
Methods for
Calculating Failure Rates in Units of
FITs
.
JESD86,
Electrical Parameters
Assessment
.
JESD94,
Application Specific
Qualification using Knowledge Based Test
Methodology.
JESD91,
Methods for
Developing Acceleration Models for Electronic
Component Failure Mechanisms
.
JEP122,
Failure
Mechanisms and Models for Semiconductor
Devices
.
JEP143,
Solid State Reliability Assessment
Qualification Methodologies.
JEP150,
Stress-
Test-Driven Qualification of and Failure
Mechanisms Associated with Assembled Solid
State Surface-Mount Components.
JESD201,
Environmental Acceptance Requirements for Tin
Whisker Susceptibility of Tin and Tin Alloy
Surface Finishes
JESD22A121,
Test Method for
Measuring Whisker Growth on Tin and Tin Alloy
Surface Finishes
3
General requirements
通用要求
3.1
Objective
目标
The objective of this procedure is to
ensure that the device to be qualified meets a
generally accepted set
of stress test
driven qualification requirements. Qualification
is aimed at components used in commercial
or industrial operating environments.
本考核流程目的是确保器件能够通过一套通用的可接受的压力
测试要求。主要考核目标是针对在
商业或工业工作环境中使用的器件
3.2 Qualification family
同族考核
While this specification may be used to
qualify an individual component, it is designed to
also qualify a
family of similar
components utilizing the same fabrication process,
design rules, and similar circuits.
JEDEC Standard No. 47I
Page 8
5.5
Device qualification requirements
(cont’d)
The family qualification may also be
applied to a package family where the construction
is the same and
only the size and
number of leads differs. Interactive effects of
the silicon and package shall be
considered in applying family
designations.
虽然本规范用于单个器件的考
核，但也可用于验证使用相同晶圆制造工艺，设计规则和相似电路
设计的同族器件。同时
也可以用于验证结构相同但只有尺寸和管脚数量不同的封装类别。
使用同
族定义时应考虑硅晶圆和封装的相互作用。
3.3 Lot requirements
批次需求
Test samples shall comprise
representative samples from the qualification
family. Manufacturing
variability and
its impact on reliability shall be assessed.
Where applicable the test samples will be
composed of approximately equal numbers
from at least three (3) nonconsecutive lots.
Other appropriate
means may be used to
evaluate manufacturing variability. Sample size
and pass/fail requirements are
listed
in Tables 1-3. Tables A and B give guidance on
translating pass/fail requirements to larger
sample
sizes.
Generic data and larger
sample sizes may be employed based upon a Chi
Squared distribution using a
total
percent defective at a 90% confidence limit for
the total required lot and sample size. ELFR
requirements shall be assessed at a 60%
confidence level as shown in Table B. If a single
unique and
expensive component is to be
qualified, a reduced sample size qualification may
be performed using 1/3
the sample size
listed in the qualification tables.
测试样品应包含同族器件中的代表性样品，
需要评估生产波动性对可靠性的影响。
在适当的情况
下，需要从至少三个非连续批次中抽取相同数量的样品，或者使用其他适
合评估生产波动性的方
法。
表
1-3
中列出了测试样本量和合格
/
不合格的要求。
表
A
和
B
给出了更大样本量情况下的合
格
/
不合格要求。
对于所有需要评估的批次和样品，可以基于卡方分布（
90%<
/p>
可信度的总失效率）
，使用通用的数据
和
更大的样品数量。
ELFR
要求按照表
B
所示的
60
％可信度进行评估。如
果要对一个独特且昂贵
的器件进行考核评估，则可以使用考核表中列出的
1/3
样本量。
3.4
Production requirements
产品要求
All test
samples shall be fabricated and assembled in the
same production site and with the same
production process for which the device
and qualification family will be manufactured in
production.
Samples need to be
processed through the full production process
including burn-in, handling, test, and
screening.
所有测试样
品需要使用相同的生产地点和流程进行制造和封装，并且生产过程中需要使用相同的
生产
工艺。
样品需要完成整个生产流程，包括老化，搬运，测试和筛选。
3.5 Reusability of test
samples
测试样品的可复用性
Devices that have been used
for nondestructive qualification tests may be used
to populate other
qualification tests.
Devices that have been used in destructive
qualification tests may not be used in
JEDEC Standard No. 47I
Page 9
5.5
Device qualification requirements
(cont’d)
subsequent qualification stresses
except for engineering analysis. Non-destructive
qualification tests are:
Early Life
Failure Rate, Electrical Parameters Assessment,
External Visual, System Soft Error, and
Physical Dimensions.
用于非破坏性考核测试的器件可以继续用其他考核测试。
除了工程分析之外，已用于破坏性考核
测试的器件不得用于随后的压
力测试。
非破坏性考核测试包括：早期失效率，电气参数测试
，外
观检查，系统软失效和物理尺寸测试。
3.6 Definition
of electrical test failure after stressing
压力测试后电气失效定义
Post-stress electrical
failures are defined as those devices not meeting
the individual device specification
or
other criteria specific to the environmental
stress. If the cause of failure is due to causes
unrelated to
the test conditions, the
failure shall be discounted.
压力测试后的电气失
效定义是指不符合器件电气参数规范或其他环境压力测试规范。
如果失败的
原因是与测试条件无关的情况造成的，则不记为失效。
3.7 Required
stress tests for qualification
考核所需要的压力测试
Table 1, Table 2, and Table
3 list the qualification requirements for new
components. Table 2 and Table 3
are
differentiated by package type, but these are not
exclusively packaging tests. Interactive effects
of the
packaging on the silicon also
drive the need for tests in Table 2 and Table 3.
Power supply voltage for
biased
reliability stresses should be
V
cc
max or
V
dd
max as defined in the
device datasheet as the
maximum
specified power supply operating voltage, usually
the maximum power supply voltage is 5% to
10% higher than the nominal voltage.
Some tests such as HTOL may allow for higher
voltages to gain
additional
acceleration of stress time. JEP122 can provide
guidance for accelerating common failure
mechanisms.
Table 4 lists the required
stresses for a qualification family or category of
change. Interactive effects from
the
unchanged aspects of both the silicon and
packaging must be assessed.
表
1
，表<
/p>
2
和表
3
列出了
新器件的考核要求。
表
2
和表
3
按封装类型区分
(
气密性和非气密性
)
，但
也不只是封装的相关测试。
硅基板和封装材料的相
互作用也需要参考表
2
和表
3
中的测试进行评
估。偏置应力可靠性测试的电源电压应该是器件数据手册
中定义的最大工作电压
Vcc
max
或
Vdd
max
（通常最大电源电压比额定工作电压高
5
％至
10
％）
。一些测试（如
HTOL
）可能允许更高的
电压来获得额外的应力加速比例
。
JEP122
可以为加速常见失效机制提供指导。
表
4
列出
了考核
器件族或类别
变更所需的压力测试。硅晶圆和封装中都未改变部分的相互作用也
必须评估。
JEDEC Standard
No. 47I
Page 10
5.5
Device qualification
requirements (cont’d)
3.8 Pass/Fail criteria
合格
/
不合格标准
Passing all
appropriate qualification tests specified in Table
1, Table 2, and Table 3, either by performing
the test, showing equivalent data with
a larger sample size, or demonstrating acceptable
generic data
(using an equivalent total
percent defective at a 90% confidence limit for
the total required lot and sample
size), qualifies the device per this
document. When submitting test data from generic
products or larger
sample sizes to
satisfy the Table 1, Table 2, and Table 3
qualification requirements of this document, the
number of samples and the total number
of defective devices occurring during those tests
must satisfy 90%
confidence level of a
Poisson exponential binomial distribution, as
defined in MIL-PRF 38535.
MIL-PRF 38535 is available for free
from
/Programs/MilSpec/?BasicDoc=MIL-
PRF-38535
. The minimum
number or samples for a given defect
level can be approximated by the formula:
N
>= 0.5 [
Χ
2
(2C+2,
0.1)] [1/LTPD
–
0.5] + C
where C = accept #, N=Minimum Sample
Size,
Χ
2
is the
Chi Squared distribution value for a 90% CL,
and LTPD is the desired 90% confidence
defect level. Table A is based upon this formula,
but in some
cases the sample sizes are
slightly smaller than MIL-PRF-38535.
<
/p>
不管是通过执行测试，还是通过大样本量给出等效的数据，或者给出可接受的通用数据（对
于所
有需要评估的批次和样品，使用等效的有
90%
置信度的总的失效百分比）
，来通过表
1
，表
2
和表
3
中指定的所有适合的考核测试。当提交来自一类产品或大样本量的测试数据来满足本文档中表
1
，
表
2
和表
3
的考核要求时，这些测试的样本数量和出
现的缺陷器件数量必须满足
90%
置信水平的
< br>泊松指数二项分布，详细定义参考
MIL-PRF
38535
。
MIL-PRF 38
535
可以通过
/Programs/MilSpec/?Ba
sicDoc=MIL-PRF-
38535
.
免费下载。给定缺陷水平的最小数量或样本可以用下式近似：
N >= 0.5
[
Χ
2
(2C+2, 0.1)]
[1/LTPD
–
0.5] + C
其中
C
=
accept
＃，
N
=
最小样品数量，
Χ
2
是
90
％置信度的卡方分布值，
LTPD
是期望的具有
90
％
置信度的缺陷级别。
表
A
基于此公式，但在某些情况下，样品数量略小于
MIL-PRF-38535
。
JEDEC Standard
No. 47I
Page 11
5.5
Device qualification
requirements (cont’d)
3.8
Pass/Fail
criteria (cont’d)
合格
/
失效标准
表
A
在
90
％的置信度下，样本量对应的最大缺陷百分比
（
LTPD
：
Lot
Tolerance Percent
Defective
批次缺陷百分比公差）
EXAMPLE: Using generic data for HTOL
with a requirement of 0 rejects from 230 samples.
If 700
samples of generic data are
available, the maximum number of failures that
will meet the qualification test
requirement is 3 failures from the
LTPD=1 column.
示例：要求测试
230
个样本中有失效
0
颗的
HTOL
测试（对应的最大缺
陷率是
1%
，置信度为
90%
）
。
如果有
700
个通用数据可用，那么符合考核测试要求的最大失效数量是
LTPD = 1
列
668
< br>对应的
3
颗失效。
4
Qualification and requalification
考核和重新考核
4.1
Qualification of a new device
新器件考核
New or redesigned products
(die revisions) manufactured in a currently
qualified qualification family may
be
qualified using one (1) wafer/assembly lot.
Electrical parameter assessment is one of the most
important tests to run.
JEDEC Standard No. 47I
Page 12
5.5
Device qualification requirements
(cont’d)
对于一个当前已考核的同族系列中，进行新设计或重新设计的产品（芯片版本）
，可以只使用一个
晶圆或者封装批次进行考核，电气特性是需要进行的最重要的测试
之一
4.2 Requalification of a changed
device
器件变更的重新考核
Requalification
of a device will be required when the supplier
makes a change to the product and/or
process that could potentially impact
the form, fit, function, quality and/or
reliability of the device. The
guidelines for requalification tests
required are listed in Table 4.
当供应商对产品或制程进行的更改影响到了器件的外形，适配
性，功能，质量或可靠性时，需要
进行器件的重新考核。
表
4
列出了所需的重新考核试验指导。
4.2.1 Process change
notification
PCN
过程变更通知
Supplier will
meet the requirements of JESD46
Changes
by Semiconductor Suppliers
对
产品和过程的变更通知，供应商需要符合
JESD46
“半导体
供应商对产品
/
工艺变更的用户通知
指
南
”
中的要求。
4.2.2 Changes requiring requalification
变更的重新考核
All product/process changes
should be evaluated against the guidelines listed
in Table 4.
所有产品和工艺变更需要按照表<
/p>
4
的指导方案进行评估
4.2
Requalification of a
changed device (cont’d)
4.2.3 Criteria
for passing requalification
重新考核的通过标准
Table 4 lists qualification
plan guidelines for performing the appropriate
Table 1, Table 2, and Table 3
stresses.
Failed devices should be analyzed for root cause
and correction; only a representative sample
needs to be analyzed. Acceptable
resolution of root cause and successful
demonstration of corrective and
preventive actions will constitute
successful requalification of the device(s)
affected by the change. The
part
and/or the qualification family can be qualified
as long as containment of the problem is
demonstrated until corrective and
preventive actions are in place.
表
4
列出了
执行适当的表
1
，表
2
和表
3
压力测试的考核计划。
对于失效器件，需要分析根本原
因并纠正
;
但是只需要分析其中一个代表性的样品即可。
失效根本原因的可接受的解决方案和成功
预防的证明以及预防措施的实施
，都可以作为受变更影响的器件重新考核说明。
只要解决和预
防
措施实施到位，证明该问题得到遏制，则该器件和同族器件都认为是合格的。
JEDEC Standard
No. 47I
Page 13
5.5
Device qualification
requirements (cont’d)
5
Qualification
tests
考核测试
5.1 General
tests
通用测试
Test details are given in
Table 1, Table 2, and Table 3. Not all tests apply
to all devices. Table 1 tests
generally
apply to design and fabrication process changes.
Table 2 tests are for non-hermetic packaged
devices, and Table 3 is for hermetic
packaged devices. Table B lists the pass/fail
requirements for
common infant
mortality levels. Table 4 gives guidance as to
which tests are required for a given process
change. Some of the data required may
be substituted by generic process or package data.
测试细节在表
1
，表
2
和表
3
中给出。但是列出的测试并不适用于所有的器件。
表
1
的测试通常
适
用于设计和晶圆制造工艺的变化。
表
2
的测试用于非气密性封装器件，表
3
用于密封封装器件。
表
B
列出了通用的早期失效率的合格
/
不合格要求。<
/p>
表
4
给出了对
于特定制程变化所需测试的指导
说明，
一些所需的数据可以使用通用工艺或封装数据替代。
5.2 Device specific tests
器件特殊测试
The following tests must be
performed on the specific device to be qualified
for all hermetic and organic
packages.
Passing or failing these tests qualifies or
disqualifies only the device under qualification
and not
the associated qualification
family:
1)
Electrostatic Discharge (ESD) - All
products - See Table 1.
2)
Latch-up (LU)
–
Required for CMOS, BiCMOS,
and Bipolar technologies. See Table 1.
3)
Electrical
Parameters Assessment - The supplier shall be
capable of demonstrating, over the
application temperature range, that the
part is capable of meeting parametric limits in
the individual
device specification or
data sheet.
所有气密封装和有机封装器件，都
必须在特定设备上进行以下测试。
通过或不通过这些测试只能
证明需要考核的器件是否通过，和同族器件没有关系：
1
）静电测试（
ESD
）
-
所有产品
-
见表
1
。
<
/p>
2
）闩锁测试（
LU
）
- CMOS
，
BiCMOS
和二极管器件。
见表
1
。
3
）电气参数评定
-
供应商需要在使用温度范围内证明该器件能够满足单个器件规范或数据表中的
参数规格。
5.3 Wearout
reliability tests
磨损可靠性测试
Qualification
family testing for the failure mechanisms listed
below must be available upon request when
a new wafer fabrication technology or a
material relevant to the appropriate wearout
failure mechanism is
to be qualified.
JP001 lists requirements for Fabrication Process
Qualification. JEP122 explains how to
project wearout lifetime for these
failure mechanisms. The following mechanisms need
to be considered,
but there may be
other mechanisms to consider based upon technology
details.
?
Electromigration; EM
JEDEC Standard No. 47I
Page 14
5.5
Device qualification requirements
(cont’d)
?
Time-Dependent
Dielectric Breakdown; TDDB or Gate Oxide Integrity
Test such as Charge to
Breakdown.
?
Hot
Carrier Injection; HCI
?
Negative Bias
Temperature Instability; NBTI
?
Stress
Migration; SM, may be performed on an actual
product.
The data, test method, calculations,
and internal criteria need not be demonstrated or
performed on the
qualification of every
new device.
当需要验证新的晶圆制造技术或
与磨损失效机制相关的材料时，要求必须提供下列失效机制的组
合考核报告。
JP001
列出了晶圆制造工艺考核的要求。
JEP122
解释了如何预测这些失效机制的磨
损寿命。
除了需要考虑以下失效机制，同时也需要根据技术细节考虑其他失效
机制。
?电迁移
;EM
?时间相关介质击穿
;
TDDB
或栅氧化层完整性测试，例如电荷击穿。
?热载流子注入
;HCI
?负偏压温度不稳定性
;NBTI
?压力迁移
;
SM
，可以在实际产品上执行。
测试
数据，测试方法，计算过程和内部标准不需要在每种新器件的考核上证明或执行。
5.4
Flammability/oxygen index
可燃
性
/
氧指数
Certificates of compliance
to UL94-0 or ASTM D2863 must be available upon
request.
根据要求需要
提供符合
UL94-0
或
ASTM
D2863
的合格证书。
5.5
Device
qualification requirements
器件考核需求
JEDEC Standard No. 47I
Page 15
5.5
Device qualification requirements
(cont’d)
Table 1
—
Device qualification tests
Requirements
Stress
High Temperature Operating
Life
< br>高温运行寿命
Early Life Failure
Rate
早期失效比例
Low Temperature Op
erating
Life
低温运行寿命
High Temperature Storage
Life
高温存储寿命
Latch-
Up
闩锁
Electrical Parameter
Assessment
电气参数测试
Human
Body Model ESD
静电测试
-
人体模式
Charged Device Model
ESD
静电测试—充电器件模式
Accelerated
Soft Error Testing
“OR”
JESD89
-1
System Soft Error Testing
S
SER
T
A
= 25 °
C
Ref.
JESD22-A108,
JESD85
JESD22-A108,
JESD
74
JESD22-A108
JESD22-A103
JESD78
JESD86
Abbv.
Conditions
T
J
>=
125 °
C
V
cc >=
V
cc
max
T
J
=125
°
C
V
cc
= V
cc
max
# Lots /
SS
per lot
3
Lots/77
units
See ELFR
< br>Table
Duration/Accept
1000
hrs/ 0 Fail
JS-001
48
1000 hrs/0 Fail
1000 hrs/0
Fail
0
Fail
T
A
per datash
eet
Classification
HTOL
ELFR
LTOL
HTSL
L
U
ED
ESD-
HBM
ESD-
CDM
T
J
<=50°
C
1 Lot/32
units
V
cc >=
V
cc
max
T
A
>=150
°
C
Class I or
Class
II
Datasheet
3
Lots/25
units
1 Lot/3
units
3
Lots/10
units
3 units
T
A
= 25
°
C
T
A
=
25
°
C
T
A
=
25 °
C
JESD22-C101
J
ESD89-2,
JESD89-3
3
units
3 units
Minimum
of
1E+06
Device Hrs
or
10 fails.
Classification
Classification
ASER
Cl
assification
a)
HTOL-
The duration listed here is generally
acceptable to qualify for the given Application
Level.
However, it does not
necessarily imply the demonstration of the
lifetime requirement for a particular use
condition. It depends on failure
mechanisms and application environments. For
example, with apparent
activation
energy of 0.7 eV
, 125 °
C
stress temperature and 55 °
C use
temperature, the acceleration factor
(Arrhenius equation) is 78.6. This
means 1000h stress duration is equivalent to 9
years of use. This might
be shorter
than the application requirement. In order to
assure adequate lifetime requirement, it would be
necessary to include Wafer Level
Reliability Test information. Wafer Level
Reliability can provide
information
about long term or intrinsic reliability of
specific wearout mechanisms, the onset to failure
time and design rule (e.g., maximum
current density). For many failure mechanisms,
such as dielectric
breakdown, elevated
voltage will provide additional acceleration and
can be used to increase effective
device hours or achieve an equivalent
life point with a shorter stress duration. Refer
to JEP122 for voltage
acceleration
models.
Nonvolatile memory
devices must be tested for proper operation after
HTOL, but
testing for data retention is
optional (see Table 1a for nonvolatile memory data
retention tests).
JEDEC
Standard No. 47I
Page 16
5.5
Device
qualification requirements (cont’d)
a
）
HTOL-
这
里列出是针对给定的使用等级的可接受的通用持续测试时间，并不意味是特定使用条
件下
的使用寿命，这取决于失效机制和使用环境。例如，当表观活化能为
0.7 eV
，
125
°
C
应力测
试温度和
55
°
C
使用温度时，加速因子（
Arrh
enius
方程）为
78.6
。这意味
着
1000
小时的应力测
试时间相当于
9
年的使用时间。可能比实际应用要求更短。为了保证足够的寿
命要求，需要进行
晶圆级可靠性测试。晶圆级可靠性可以提供关于具体磨损，开始失效时
间和设计规则（例如最大
电流密度）的长期或固有可靠性信息。对于许多失效机制，例如
绝缘击穿，较高的电压可以提供
额外的测试加速，可用于增加有效的器件测试时间或在较
短的应力测试时间下实现等效寿命。有
关电压加速度模型，请参阅
JEP122
。非易失性存储器件在
HTOL
之后必须进行完整的功能测试，
但数据保持测试是可选的（见表
1a
非易失性存储器数据保持测试）
。
b)
ELFR
-
Several methods can be used to
calculate the Early Life Failure Rate (ref.
JESD74). The objective
of ELFR is to
measure the failure rate in the first several
months or year of operation.
Knowledge of the life distribution is
generally required to accurately predict ELFR.
Equivalently, Table B
can be used to
determine sample sizes to satisfy a particular FPM
(cumulative failures) target. Voltage and
temperature acceleration may be used to
further accelerate effective unit hours.
Nonvolatile memory
devices must be
tested for proper operation after ELFR, but
testing for data retention is optional (see Table
1a for nonvolatile memory data
retention tests).
b
）
ELFR
–
有多种方法可以计算早期失效率（
参考文献
JESD74
）
。
ELFR
的目标是评估产品初
期几个月或第一年
的失效率。
通常需要了解器件的寿命分布以准确预测
ELFR
。
等同地，
表
B
用于确定满足特定
FPM
（累
积失效）目标的样本数量。
可以使用电压和温度加速来增加有效测试时间。
在
ELFR
测试之
后，必须
测试非易失性存储器件是否正常工作，但数据存储测试是可选的（见表
1a
非易失性
存储器数据保留测试）
。
< br>
c)
LTOL
–
This
requirement is aimed at Hot Carrier Degradation
and may be satisfied by appropriate wafer
level data as specified in JP001. This
test is particularly useful when the wafer level
data cannot
demonstrate adequate life.
This test should be run at the maximum frequency
of the device with speed
parameters
data logged. Nonvolatile memory devices must be
tested for proper operation after LTOL, but
testing for data retention is optional
(see Table 1a for nonvolatile memory data
retention tests).
c
）
LTOL -
< br>这个测试要求是针对热载流子退化，可以通过
JP001
中规定的适当的晶圆级数据来
评估，特别是当晶圆级的测试数据无法证明足够的使用寿命
时。
该测试应该在器件的最高工
作频
率下运行，并记录运行速度参数数据。
在
LTOL
之后，非易失性存储器件必须经过正常
测试，但测
试数据保留是可选的（请参阅表
1a
以了解非易失性存储器数据
保留测试）
。
d)
HTSL
–
High
temperature storage may be accelerated by
utilizing a higher temperature; however care
must be taken that new failure
mechanisms are not introduced such as Kirkendal
V
oiding at too high a
temperature or suppressing failure
mechanisms such as stress migration at
temperatures above 180 °
C.
Alternatively, this test may be
performed at the wafer level if packaged device
reliability has been
addressed with
generic data. Nonvolatile memory devices must be
tested for proper operation after HTSL,
but testing for data retention is
optional (see Table 1a for nonvolatile memory data
retention tests).
JEDEC Standard No. 47I
Page 17
5.5
Device qualification requirements
(cont’d)
d
）
HTSL
–
可以利用更高的温度来加速高温储存测试时间
;
但必须注意不要引入新的失效机制，
例如温度过高的
Kirkendal
空洞，或者温度超过
180
°
C
时被抑制的应力迁移等失效机制。如
果通用数据证明了封装器件的可靠性问题，则可以在晶圆级执行此测试。
<
/p>
非易失性存储器件
经过
HTSL
后必须经过正常功能测试，但测试数据保存测试是可选的（见表
1a
非易失性存储
器数据保留测试）
。
e)
LU
–
Verify V
cc
overvoltage and
I/O trigger current resistance to latch-up per
JESD78.
e
）
LU -
验证
Vcc
过压和
I / O
触发电流是否符合
JESD78
的闩锁要求。
f)
ED
–
This study is to be performed on key device
parameters, it is not aimed at all datasheet
parameters.
本研究将在关键器件参数上执行，它不针对所有数据表参数。
g)
ESD-
HBM
Classification of Human body Model
ESD resistance
h)
ESD-
CDM
Classification of Charge Device
model ESD resistance.
i)
ASER
Accelerated
alpha particle and beam soft error testing may be
utilized together to project
the field
soft error rate. For parts without
B
10
in the process, the only
beam soft error testing required
is
high energy neutron or proton soft error testing;
thermal neutron soft error beam testing is not
required for such parts. This test is
required for devices with a significant portion of
the circuit
utilizing volatile memory
elements or latches. Generic data taken on
products or test devices with
similar
memory elements or latches and equivalent critical
charge may be substituted.
i
）
ASER
加速的
α
粒子和束软错误测试可以一起使用以计算应用中的
软失效率。
对于在此测
试中没有
B10
的部分，唯一需要的束软错误测试是高能中子或质子软失效测
试
;
这种部件不需
要热中子软错误测试。
对于电路中使用易失性存储器元件或锁存器的重要部分来说，该测试
是必需的。
采用相似存储器元件或锁存器或等效关键电荷
的产品或器件上的通用数据可以相
互替代
备注：软错误是指高能粒子与硅元素之间的相互作用而在半导体中造成的随机、临时的状态
< br>改变或瞬变，详细可以参考
JESD89
，主要用于
SRAM
和
DRAM
的评估考核
j)
SSER
System soft
error testing requires enough device hours to be
accumulated to produce 10
failures or
at least 1E6 device hours must be accumulated.
High altitude testing may be used to
accelerate this stress. This test may
be utilized in lieu of or in addition to
accelerated soft error testing.
Generic data taken on products or test
devices with similar memory elements or latches
and
equivalent critical charge may be
substituted.
SSER
系统软错误测试需要足够的累积产生
10
次故障的时间，或者
至少累计
1E6
设备小时。
高海拔测试可以用来加速这种压力测试。
这个测试可以用来代替或者加速软错误测试。
采用
相似存储器元件或锁存器或等效关键电荷的产品或器件上的通用数据可以相
互替代。
JEDEC Standard No. 47I
Page 18
5.5
Device qualification
requirements (cont’d)
表
1a -
非易失性存储器件的附加认定测试
a)
UCHTDR
–
Uncycled nonvolatile memories data
retention failure mechanisms are generally
accelerated by temperature and are
modeled using the Arrhenius Equation for
acceleration. The
duration listed is
generally acceptable for qualification but do not
necessarily demonstrate the
retention
requirement for a particular use condition, which
depends on failure mechanisms,
acceleration factors and application
environment. If the application requirement does
not match the
UCHTDR test’s retention
values then a knowledge
-based
qualification should be followed (see
JEDEC Standard No. 47I
Page 19
5.5
Device qualification requirements
(cont’d)
JESD94). For devices specified to have
some non-zero bit error rate, bit errors may not
be counted
towards device failure but
must be shown to meet the bit error rate
specification (see JESD22-A117).
a
）
UCHTDR -
不进行循环擦写的非易失性存储器数据保持失效机制一般可以通过高温进行加速，
使用阿伦尼乌斯方程来计算加速倍率。表格中所列出的持续测试时间一般是可以接受的，但并
< br>不一定可以证明在特定使用条件下的数据保持要求，这取决于失效机制、加速因子和使用环境。
< p>如果使用环境的要求与
UCHTDR
测试的数据保
留时间不匹配，那么应该遵循一个基于可靠性
知识体系的考核标准
(
参见
JESD94)
。对于说明
具有一定比例字节失效率的器件，单比特失效
可以不记为器件失效，但必须证明在比特失
效率的规范以内
(
参见
JESD22-
A117)
。
b)
NVCE
See Figure 1 for linked flow for NVCE,
PCHTDR and LTDR. Half of the devices are cycled
at
room temperature and half at
elevated temperature. Quantity of Cycling:
Cycling should be performed to
the max
spec. cycle count on 50% of cells and to 10% of
max spec. cycle count on the other 50% of cells
when this is possible within 500 hours.
For large memories where this would be impossible,
the total
program/erase operations are
to be the number possible in 500 hours. This will
be accomplished by
reducing the
fraction of cells cycled to max spec. and
increasing the fraction cycled to 10% of max spec.
In some cases it will be necessary to
cycle some fraction of cells to less than 10% of
max spec. to ensure
that all cells
receive some cycling. At least one-third of the
operations should be devoted to cycling blocks
to 100% of maximum specification. For
multi-block memories, at least one block of each
device must be
cycled to the max. spec.
cycle count, regardless of the time required.
Such cycling conditions are
generally
acceptable also for system implementing wear
leveling; otherwise, a knowledge based
qualification can be implemented.
Delays between Cycles: The supplier may specify
that cycling not
exceed a certain rate
per day or that delays or bakes be inserted
between cycles, to avoid overstress due to
unrealistic conditions or to emulate
delays expected in intended application, subject
to four constraints.
First, the
quantity of cycling is for 500 hours of actual
cycling operations, not counting inserted delays.
Second, inserted delays must be
distributed per the guideline in JESD22-A117.
Third, for roomtemperature
cycling, no
high-temperature delays are to be inserted.
Fourth, for high-temperature cycling, the delays
plus the cycling time itself must not
add up to more than 500 hours at 85 °
C
(longer delays acceptable at
lower
temperatures per JESD22-A117, 4.1.2.4). These
delays do not necessarily demonstrate the effect
that
would be seen with a particular
use condition. For example, with apparent
activation energy of 1.1 eV for
dielectric charge detrapping, the delay
durations are equivalent to 1.5 years of cycling
at 55 °
C. An
application
condition with less delay would be more severe
than is represented by the qualification delays
specified above. If application use
conditions deviate considerably from the cycle
counts or equivalent
times described
above, then an application-specific qualification
methodology can be pursued per JESD94.
For devices operated with Bad Block
Management and specified to have a non-zero
badblock rate, a unit
with blocks
failing program/erase is to be counted as a
failure if the number of such blocks exceeds the
allowed bad-block
specification
(see
JESD22-A117, 2.5). For devices specified to have
some non-zero bit
read error rate, bit
errors are not to be counted towards device
failure but must be shown to meet the bit
error rate specification (see
JESD22-A117, 2.8, and 5.2).
图
1
是<
/p>
NVCE
（非易失性存储器循环擦写寿命）
，
PCHTDR
（循环擦写后高温存储寿命）和
LTDR
（低温数据存储寿命）的测试顺序流程。一半器件在室温下循环，一
半在高温下循环。
循环次数：如果预期测试时间在
500
小时以内，尽量对
50%
的存储单元进行最大
寿命的擦写，
另外
50%
存储单元循环
擦写到最大寿命的
10%
。对于大容量的存储器件，如果不可能
在
500
JEDEC Standard No. 47I
Page 20
5.5
Device qualification
requirements (cont’d)
小时内完成所有的编程
/
擦除操作。可以通过逐步减少完成最大规格寿命测试的存储单元比例，
并逐
步增加测试最大寿命
10%
的存储单元比例。在某些情况下，一
部分存储单元有必要只测
试
10% SPEC
< br>以下的寿命，来确保所有存储单元都能接受一些循环测试。至少三分之一的测试
操
作应该用于达到最大规格
100
％的区块循环测试。对于多区块
存储器，无论需要多少测试时
间，每个器件的至少一个区块必须达到最大循环寿命次数规
范。这种循环测试条件也是可以
用于系统磨损测试中；否则，必须实施基于可靠性知识体
系的考核。
循环之间的延时：在以下四个条件约束下，供应商
可以规定循环次数不超过多少
/
每天，来避
免由于不切实际的条件造成的过度应力；或者在循环擦写之间插入延时或烘烤，来模拟预期
< br>使用环境中出现的延时。
首先，循环次数为
500
小时内（不包括插入的延时）进行的实际循环次数。
其次，插入的延时必须按照
JESD22-A117
中的准则进行分配。
第三，对于室温循环，不要插入高温延时。
< br>第四，对于高温循环，延时加上循环时间在
85
摄氏度下
不能超过
500
小时（在
JESD22
-
A117,4.1.2.4
中规定，低温下可接受更长的延时
时间）
。
这些延时并不一定可以说明
在特定使用条件下会出现的效果。例如，对于活化能为
1.1eV
的电
介质电荷逃逸，延时测试时间相当于在
55
℃下循环
1.5
年。低延时应用条件会比上述代表性
的延时条件更加严苛。如果应用使用条件严重偏离了上述的擦写次数或等效时间
，可按照
JESD94
的要求采用特定应用考核方法。对于说明拥有
“
坏块管理
”
并且具有一定字节失效比例
的器件，如果
编程擦写失效的单元中，坏块数量超过了允许的规格，
这个部
件将被计为失败
（请参阅
JESD22- A117,2.5<
/p>
）
。对于详细说明的具有某些一定位读取错误率的器件，位错误可
以不计入器件故障，但必须证明失效率符合器件规范（参见
JE
SD22-A117,2.8
和
5.2
）
。
c)
PCHTDR
See Figure 1 for linked flow for NVCE,
PCHTDR and LTDR. The NVCE devices cycled
at elevated temperature are placed in
high-temperature retention bake. Two options are
given, either of
which is acceptable
for qualification, and for each option two bake
durations. The longer of the two
durations is to be applied to the
blocks cycled to
10% of the max. spec.
cycles. The shorter of the two
is to
be applied to blocks cycled to 100% of max. spec.
cycles. For example option 2 requires that blocks
cycled to
10% of max. spec.
cycles retain data for 100 hours of 125
°
C (FG-CT)/100 °
C (PCM)
bake,
and blocks cycled to 100% of max.
spec. cycles must retain data for 10 hours of 125
°
C (FG-CT)/100 °
C
(PCM) bake. The durations listed are
generally acceptable for qualification but do not
necessarily
demonstrate the retention
requirement for a particular use condition, which
depends on failure mechanisms
and
application environments. For example, with
activation energy of 1.1 eV for dielectric charge
detrapping, 125 °
C stress
temperature (option 2) and 55 °
C use
temperature, the acceleration factor
(Arrhenius equation) is 939. Bake time
is then equivalent to 11.3 years for 10% of max.
spec. cycles and
1.1 years for 100% of
max. spec. Retention lifetime necessary in use
will be less than total product
lifetime, because the PCHTDR
requirement is a sequential reliability stress
that is preceded by up to one
lifetime’s worth of endurance cycling
(NVCE). If the application requirement does not
match these
retention values, or the
technology has different activation energy, then a
knowledge-based qualification
should be
followed (see JESD94). For devices specified to
have some non-zero bit error rate, bit errors
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