-
Location: Shanghai
Responsibility:
Participate
IP
and
SoC
level
architecture
definition,
derive
functional
and design specifications and analyze
feasibility of technical and
architectures.
Participate
Bus/Display/Video/DFX
IP
design.
Work
on
world
most
sophisticated GPU DFT design:
SCAN/MBIST/DV and DFX innovative.
Implement
design
with
Verilog
to
achieve
specification
goals.
Simulate
and debug the codes in coding stage.
Go through the FE design flow to
deliver qualified netlist. Feedback
to
Physical Design team to help to close timing and
check floorplan.
Maintain and update
DFT design flow.
Verify the functional
correctness of Bus/Display/Video/DFX IPs and
Graphic North Bridge from IP level to
SoC level using advanced DV
methodologies.
Write
ASIC
specific
part
of
test
plan.
Debug
regression
failures and
identify the cause.
Maintain
design
&
verification
environment
built
with
C/C++/SystemC/System
Verilog
(OVM)/Perl.
Develop
System
Verilog
(OVM)
random
sequences
and
methods.
Develop
scripts
to
improve
flow
efficiency.
Create
test
libraries,
test
API,
simulation
models.
Solve
flow issues.
Working as the technical point of
contact on the ASIC area.
Requirement:
Master or Ph.D of EE & CS.
Candidate of design engineer must be
proficient in Verilog coding,
debugging
and modeling.
Candidate
of
design
engineer
must
be
skilled
in
RC/DC,
PT,
Formality/LEC
and have
knowledge of synthesis and timing analysis.
Candidate of design verification
engineer must be fluent in C/C++,
familiar with Verilog and has basic
understanding about RTL design.
Must
be
organized,
enthusiastic
self-starter
and
have
the
ability
and
desire to work as a team.
Should have knowledge of Computer
architecture.
Should be familiar with
mainstream EDA tools for design, simulation
and debug such as ncsim/vcs / verdi.
Should
be
familiar
with
verification
methodologies
for
from
block
level
to SoC level.
Should be familiar with shell/perl/tcl
programming in linux OS.
Should be
familiar with P&R and Manufacture tech.
Should be good at documentation.
Will be a big plus if having PCIe /
Display / Video /DFT experience.
Have
project experience during university education.
Should
have
good
English
hearing,
speaking,
reading
and
writing
capabilities.
Strong
passion in achievement and career development.
A self-motivated team player.
J006: GPU Design
Verification Engineer
Location:
ShanghaiResponsibility:
Understand the
architecture of the chip and functional block
being
designed.
Develop
C/C++ model for simulation.
Develop
test bench and monitors for DUT.
Compose
test
plan
and
validation
vectors
to
ensure
functional
completeness.
Debug function/performance bugs of
graphics chips.
Requirement:
Master or above degree.
Major in Micro-E or related, Electronic
Engineer, Computer Science,
Mathematics. Communication.
Meet one of the following
requirements1) Good at C/C++ programming
and debug2) Good at Verilog coding
and debugging
Familiar with unix/linux
environment and scripts programming.
Strong problem solving skills.
Computer architecture and Operating
System is a plus.
Computer graphic
basic knowledge is a plus.
Experience
with design verification methodologies is a plus.
Proficient English and Mandarin
(listening, writing and speaking).
Have
project experience during university education.
Strong passion in achievement and
career development.
A self-motivated
team player.
J007: GPU Design Engineer
Location: ShanghaiResponsibility:
Develop micro-architecture
specification for GPU blocks.
Develop
RTL code for GPU blocks in Verilog HDL.
Responsible
for
Front-End
chip
implementation
including
design,
implementation
and
execution
of
the
flow
that
starts
with
RTL
code
and
ends
with
the
delivery
of
a
netlist
package
ready
for
physical
design.
Responsible
for
ASIC
design
methodology
and
flow
development,
interfacing with EDA vendors on
technology.
Requirement:
Master or above degree.
Major in Micro-E or related, Electronic
Engineer, Computer Science,
Mathematics. Communication.
Familiar with Verilog HDL coding and
ASIC Frond-End implementation
flow.
Familiar with unix/linux and scripts
(tcl, perl, python etc.).
Strong task-
based organization skills.
Computer
architecture and computer arithmetic (a plus).
Computer graphic basic knowledge (a
plus).
Experience with Database
technologies
and
database-
driven custom
web
application development (a plus).
Proficient English and Mandarin
(listening, writing and speaking).
Have
project experience during university education.
Strong passion in achievement and
career development.
A self-motivated
team player.
Intel????HW architecture Concept
Engineer
Description
'As a
member of Concept Engineering Hardware
Architecture team that
specifies the
solutions for 2.5G and 3G handset
baseband chips, the candidate will be
responsible for the Digital
Baseband
portion of the solution. This includes
the
overall
HW
architecture
meeting
the
functionality
and
performance
specified by the
System Requirements. The