-
AT89C52 internal
structure analysis
Description
The
AT89S52
is
a
low-power,
high-performance
CMOS
8-bit
microcontroller
with
8Kbytes
of
in-system
programmable
Flash
memory.
The
device
is
manufactured
using
Atmel?s
high
-density
nonvolatile
memory
technology
and
is
compatible
with
the
industry-standard
80C51
instruction
set
and
pinout.
The
on-chip
Flash
allows
the
programmemory
to
be
reprogrammed
in-system or by a conventional
nonvolatile memory programmer. By combining a
versatile 8-bit CPU with in-system
programmable Flash ona monolithic chip, the
Atmel
AT89S52 is
a
powerful
microcontroller
which
provides
a
highly-flexible
and
cost-effective
solution
to
many
embedded
control
applications.
The
AT89S52 provides the following standard
features: 8K bytes of
Flash, 256 bytes
of
RAM,
32
I/O
lines,
Watchdog
timer,
two
data
pointers,
three
16-bit
timer/counters, a
six-vector two-level interrupt architecture, a
full duplex serial
port, on-chip
oscillator,and clock circuitry. In addition, the
AT89S52 is designed
with static logic
for operationdown to zero frequency and supports
two software
selectable power saving
Idle Mode stops the CPU while allowing the
RAM,
timer/counters,
serial
port,
andinterrupt
system
to
continue
functioning.
The
Power-down
mode
saves
the
RAM
contentsbut
freezes
the
oscillator,
disabling all other chip functions
until the next interruptor hardware
reset.
Pin Description
VCC
Supply voltage.
GND
Ground.
Port
0
Port 0 is an 8-bit open drain
bidirectional
I/O port. As anoutput
port, each
pin can sink eight TTL
inputs. When 1sare written to port 0 pins, the
pins can be
used as 0 can also be
configured to be the multiplexed
loworder address/data bus during
accesses to external program and data memory.
In this mode, P0 has internal 0 also
receives the code bytes during
Flash
programming
and
outputs
the
code
bytes
during
program
al pullups are
required during program verification.
Port 1
Port
1
is
an
8-bit
bidirectional
I/O
port
with
internal
Port
1
output
buffers
can
sink/source
four
TTL
1s
are
written
to
Port
1
pins, they are pulled high by the
internal pullups and can be used as inputs. As
inputs,Port
1
pins
that are
externally
being
pulled low
will
source
current
(IIL)
because of the
internal pullups. In addition, P1.0 and P1.1 can
be configured to
be
the
timer/counter
2
external
count
input
(P1.0/T2)
and
the
timer/counter
2
trigger
input
(P1.1/T2EX),
respectively,
asshown
in
the
following
1
also
receives
the
low-order
address
bytes
duringFlash
programming
and
verification.
Port 2
Port
2
is
an
8-bit
bidirectional
I/O
port
with
internal
Port
2
output
buffers
can
sink/source
four
TTL
1s
are
written
to
Port
2
pins,
they
are
pulled
high
bythe
internal
pullups
and
can
be
used
as
inputs.
As
inputs,Port
2
pins
that
are
externally
being
pulled
low
will
sourcecurrent
(IIL)
because
of
the
internal
2
emits
the
high-
order
address
byte
during
fetchesfrom
external
program
memory
and
during
accesses
toexternal
data
memory
that
use 16-bit
addresses
(MOVX
@DPTR).
In
this
application, Port
2
uses strong internal pull-
ups when emitting 1s. During accesses to external
data
memory that use 8-bit addresses
(MOVX @ RI), Port 2 emits the contents of the
P2 Special Function Register. Port 2
also receives the high-order address bits and
some control signals during Flash
programming and verification.
Port 3
Port
3
is
an
8-bit
bidirectional
I/O
port
with
internal
Port
3
output
buffers
can
sink/source
four
TTL
1s
are
written
to
Port
3
pins, they are pulled high by the
internal pullups and can be used as inputs. As
inputs,Port
3
pins
that are
externally
being
pulled low
will
source
current
(IIL)
because of the 3 also
serves the functions of various special features
of
the
AT89S52,
as
shown
in
the
following
3
also
receives
some
control signals for
Flash programming and verification.
RST
Reset input. A high on
this pin for two machine cycles while the
oscillator is
running resets the
device. This pin drives High for 96 oscillator
periods after the
Watchdog times
DISRTO bit in SFR AUXR (address 8EH) can be used
to disable this feature. In the default
state of bit DISRTO,the RESET HIGH out
feature is enabled.
ALE/PROG
Address Latch Enable (ALE) is an output
pulse for latching the low byte of
the
address
during
accesses
to
external
memory.
This
pin
is
also
the
program
pulse
input
(PROG)
during
Flash
normal
operation,
ALE
is
emitted
at
a
constant
rate
of
1/6
the
oscillator
frequency
and
may
be
used
for
external
timing
or
clocking
purposes.
Note,
however,
that
one
ALE
pulse
is
skipped
during
each
access
to
external
data
desired,
ALE
operation
can
be
disabled
by
setting
bit
0
of
SFR
location
8EH. With
the
bit
set,
ALE
is
active only during a MOVX or MOVC
instruction. Otherwise, the pin is weakly
pulled high. Setting the ALE-disable
bit has noeffect if the microcontroller is in
external execution mode.
PSEN
Program
Store
Enable
(PSEN)
is
the
read
strobe
to
externalprogram
the
AT89S52
is
executing
code
from
external
program
memory,
PSEN
is
activated
twice
each
machine
cycle,
except that two PSEN
activations
are skipped
during each access to external data
memory.
EA/VPP
External Access Enable. EA must be
strapped to GND in order to enable the
device to fetch code from external
program memory locations starting at 0000H
up
to
,
however,
that
if
lock
bit
1
is
programmed,
EA
will
be
internally
latched
on
should
be
strapped
to
VCC
for
internal
program
pin also receives
the 12-volt programming enable voltage (VPP)
during Flash programming.
XTAL1
Input
to
the
inverting
oscillator
amplifier
and
input
to
the
internal
clock
operating circuit.
XTAL2
Output from the
inverting oscillator amplifier.
Special Function Registers
A
map
of
the
on-chip
memory
area
called
the
Special
FunctionRegister
(SFR) space is shown in Table that not
all of the addresses are occupied,
and
unoccupied addresses may not be implemented on the
accesses to
these addresses will in
general return random data, and write accesses
will have
an
indeterminate
software
should
not
write
1s
to
these
unlisted
locations,since
they
may
be
used
in
future
products
to
invokenew
features.
In
that case, the reset or
inactive values of the new bits will always be 0.
Timer 2 Registers:
Control and status bits are contained
in registers T2CON (shown in Table 2)
and
T2MOD
(shown
in
Table
3)
for
Timer
2.
The
register
pair
(RCAP2H,
RCAP2L) are the
Capture/Reload registers for Timer 2 in 16-bit
capture mode or
16-bit auto-reload
mode.
Interrupt Registers:
The individual interrupt enable bits
are in the IE register. Two priorities can
be set for each ofthe six interrupt
sources in the IP register.
Memory
Organization
MCS-51
devices
have
a
separate
address
space
for
Program
and
Data
Memory.
Up
to
64K
bytes
each
of
external
Program
and
Data
Memory
can
be
addressed.
Program Memory
If
the
EA
pin
is
connected
to
GND,
all
program
fetches
are
directed
to
external the AT89S52, if EA is
connected to VCC, program fetches
to
addresses 0000H through 1FFFH are directed to
internal memory and fetches
to
addresses 2000H through FFFFH are to external
memory.
Data Memory
The
AT89S52 implements 256 bytes of on-chip RAM. The
upper 128 bytes
occupy
a
parallel
address
space
to
the
Special
Function
Registers.
This
means
that
the
upper
128
bytes
have
the
same
addresses
as
the
SFR
space
but
are
physically
separate
from
SFR
space.
When
an
instruction
accesses
an
internal
location
aboveaddress
7FH,
the
address
mode
used
in
the
instructionspecifies
whether
the
CPU
accesses
the
upper
128
bytes
of
RAM
or
the
SFR
space.
Instructions
which
use
direct
addressing
access
of
the
SFR
example,
the
following
direct
addressing
instruction
accesses
the
SFR
at
location
0A0H
(which is P2). MOV 0A0H, #data
Instructions that use indirect
addressing access the upper 128 bytes of RAM.
For
example,
the
following
indirect
addressing
instruction,
where
R0
cont
ains
0A0H,
accesses the data byte at address 0A0H, rather
than P2 (whose address is
0A0H).
MOV @R0, #data
Note that
stack operations are examples of
indirectaddressing, so the upper
128
bytes of data RAM are availableas stack space.
Watchdog Timer
(One-time
Enabled with Reset-out)
The WDT is
intended as a recovery method in situationswhere
the CPU may
be
subjected
to
software
upsets.
The
WDT
consists
of
a
13-bit
counter
and
the
Watchdog
Timer Reset (WDTRST) SFR. The WDT is defaulted to
disable from
exiting reset. To enable
the WDT, a user must write
01EH and
0E1H in sequence to the WDTRST register (SFR
location 0A6H).
When
the
WDT
is
enabled,
it
will
increment
every
machine
cycle
while
the
oscillator is running. The WDT timeout
period is dependent on the external clock
frequency.
There
is
no
way
to
disable
the
WDT
except
through
reset
(either
hardware reset or
WDT overflow reset). When WDT overflows, it will
drive an
output RESET HIGH pulse at the
RST pin.
Using the WDT
To
enable the WDT, a user must write 01EH and 0E1H in
sequence to the
WDTRST
register
(SFR
location
0A6H).When
the
WDT
is
enabled,
the
user
needs
to
service
it
by
writing
01EH
and
0E1H
to
WDTRST
to
avoid
a
WDT
13-bit
counter
overflows
when
it
reaches
8191(1FFFH),
and
this
will
reset the device. When the WDT is enabled, it will
increment every machine
cycle while the
oscillator is running. This means the user must
reset the WDT at
least
every
8191
machine
cycles.
To
reset
the
WDT
the
user
must
write
01EH
and
0E1H
to
WDTRST.
WDTRST
is
a
write-only
register.
The
WDT
counter
cannot
be
read
or
written.
When
WDT
overflows,
it
will
generate
an
output
RESET
pulse
at
the
RST
pin.
The
RESET
pulse
duration
is
96xTOSC,
where
TOSC=1/FOSC. To make the best use of
the WDT, it should be serviced in those
sections
of
code
that
will
periodically
be
executed
within
the
time
required
to
prevent a WDT reset.
WDT During Power-down and Idle
In Power-down mode the oscillator
stops, which means the WDT also stops.
While in Power-down mode, the user does
not need to service the WDT. There
are
two
methods
of
exiting
Power-down
mode:
by
a
hardware
reset
or
via
a
level-
activated external interrupt which is enabled
prior to
entering
Power-down
mode.
When
Power-
down
is
exited
with
hardware
reset,
servicing
the
WDT
should
occur
as
it
normally
does
whenever
the
AT89S52 is reset. Exiting Power-down
with an interrupt is significantly different.
The
interrupt
is
held
low
long
enough
for
the
oscillator
to
stabilize.
When
the
interrupt
is
brought
high,
the
interrupt
is
serviced.
To
prevent
the
WDT
from
resetting
the
device
while
the interrupt pin
is held low,
the
WDT
is not
started
until the interrupt
is pulled high. It is
suggested that the WDT be reset during
the
interrupt service for the interrupt
used to exit Power-down ensure that
the WDT does not overflow within a few
states of exiting Power-down, it is best
to reset the WDT just before entering
Power-down mode. Before going into the
IDLE
mode,
the
WDIDLE
bit
in
SFR
AUXR
is
used
to
determine
whether
the
WDT
continues to
count if enabled. The WDT
keeps counting during IDLE (WDIDLE bit = 0)
as
the
default
state.
To
prevent
the
WDT
from
resetting
the
AT89S52
while
in
IDLE
mode,
the
user
should
always
set
up
a
timer
that
will
periodically
exit
IDLE, service the WDT,
and reenter IDLE mode. With WDIDLE bit enabled,
the
WDT
will
stop
to
count
in
IDLE
mode
and
resumes
the
count
upon
exit
from
IDLE.
UART
The
UART
in
the
AT89S52
operates
the
same
way
as
the
UART
in
the
AT89C51
and
AT89C52.
For
further information on
the
UART
operation,
refer
to
the
ATMEL
Web
site
().
From
the
home
page,
select
?Products?,then
?8051
-
Architecture
Flash
Microcontroller?,
then?Product
Overview?.
Timer
0 and 1
Timer 0 and Timer 1 in the
AT89S52 operate the same wayas Timer 0 and
Timer
1
in
the
AT89C51
and
AT89C52.
Forfurther
information
on
the
timers?
operation, refer to the ATMEL Web site
(). From the home
page,
select
?Products?,
then
?8051
-
Architecture
Flash
Microcontroller?,
then
?Product Overview?.
Timer 2
Timer
2
is
a
16-bit
Timer/Counter
that
can
operate
as
either
a
timer
or
an
event
counter. The type of operation is selected by bit
C/T2 in the SFR T2CON
(shown in Table
2). Timer 2 has three operating modes: capture,
auto-reload (up
or
down
counting),
and
baud
rate
generator.
The
modes
are
selected
by
bits
in
T2CON, as shown in Table
3. Timer 2 consists of two 8-bit registers, TH2
and
TL2. In the Timer function, the TL2
register is incremented every machine cycle.
Since a machine cycle consists of 12
oscillator periods, the count rate is 1/12 of
the oscillator frequency.
In
the Counter function, the register is incremented
in response to a 1-to-0
transition
at
its
corresponding
external
input
pin,
T2.
In
this
function,
the
external input is
sampled during S5P2 of every machine cycle. When
the samples
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