competition-网纹蟒
一直不清楚
FPGA
中
Speed Grade
的可选值的大小与
FPGA
速率是成正比还是反比关系，
我
对其不解。如下文
中的提问者，所以今天
GOOGLE
了一下，找到了答案，如下
英文。
简单的说
FPGA
的
speed grade
是一个相对标准，在
现代版的（
XILINX
）
FPGA
中，
Speed
Grade
的值越大其速率越高，具体说详解下文（回答问题的
2
人均为
Xilinx
的员工）：
ASK
：
Can anyone please explain what a speed
grade is?
If i tell
you my
bicycle has a speed grade of 29, you’ll probably
say something like: “Good for
you.”,
but you wouldn’t have a clue about what i just
said.
So, can you explain
to me how i should see the speed grades.
What do they stand for?
Who
defines the speed grades?
Can i
compare the speed grades between manufacturers?
I can’t seem to be able to find
anything about the subject anywhere…
ANSWER 1
：
There is no consistent definition of a
speed grade for all devices. Even for Xilinx,
speed grades
mean different things
depending on if you are referring to a FPGA or a
CPLD. For CPLDs, speed
grades represent
the time it takes for logic to go through the
device (eg. in <= out). So a -10 device
means that the device is guaranteed to
send a signal from an input pin thru to an output
pin in
under 10 nS. So for CPLDs, the
lower the number, the faster the part is. This is
standard for
CPLDs across all vendors
so this can be used for device comparison
purposes.
However for FPGAs, they don’t
use the same definition for speed
grade.
Originally speed grades
for FPGAs represented the time through
a look up table
but now the
speed grade doesn’t
actually repesent a
timing path. I am not sure if it is the same for
other vendors, but
for Xilinx
FPGAs higher numbers are
faster
.
Each speed grade
increment is ~15% faster than the one
before it
. So a -5 is 10%
faster than a -4 speed grade.
Arthur
ANSWER 2
：
As Arthur indicated, it is a relative
term that is really dependent on the specific
family:
-for CPLDs, it is generally
pin-to-pin delays in nanoseconds (lower # =
faster)
-for
old Xilinx
FPGAs
(pre-Virtex),
lower #
was faster
-for
modern (Virtex and later)
FPGAs
,
the higher # is
faster.