AT45DB321中英对照

首先最重要的位（

MSB

）传来的。

缓冲区寻址标准的

DataFlash

页面大小（

528

字节）中引用

数据表使用的术语

BFA9 - BFA0

表示

10

位地址需要

D ESIG-

内特缓冲区内的字节地址。使用主内存寻址引用

术语

PA12 - PA0

和

BA9 - BA0

，其中

PA12 - PA0

表 示

13

位地址

需要指定一个网页地址和

BA9 - BA0

< br>表示需要

10

位地址

在页面中指定一个字节的地址。

为“

Power2

”二进制页大小（

512

字节）的缓冲区寻址中引用

使用常规术语

BFA8 - BFA0

来表示的

9

位地址的数据表

需要指定缓冲区内的一个字节的地址。主存储器寻址引用

使用的术语

A21 - A0

，

A21 - A9

代表的

13

个地址位需要

DESIG-

内特页面地址和

A8 - A0

表示< /p>

9

位地址需要指定一个字节

一个页面内的地址

6. Read Commands

By specifying the appropriate opcode, data can be read from the main memory or from either

one of the two SRAM data buffers. The DataFlash supports RapidS protocols for Mode 0 and

Mode 3. Please refer to the

“Detailed Bit

-

level Read Timing” diagrams in this datasheet for

details on the clock cycle sequences for each mode.

6

。读命令

通过指定适当的操作码，可以将数据从主存储器读出，或从任一

其中的两个

SRAM

数据缓冲区。数据 闪存支持模式

0

和急流协议

模式

3

。请参阅“详细位级读时序”图本数据表

为每个模式的时钟周期序列的详细信息。

6.1 Continuous Array Read (Legacy Command: E8H): Up to 66 MHz

By supplying an initial starting address for the main memory array, the Continuous Array Read

command can be utilized to sequentially read a continuous stream of data from the device by

simply providing a clock signal; no additional addressing information or control signals need to

be provided. The DataFlash incorporates an internal address counter that will automatically

increment on every clock cycle, allowing one continuous read operation without the need of

additional address sequences. To perform a continuous read from the DataFlash standard page

size (528 bytes), an opcode of E8H must be clocked into the device followed by three address

bytes (which comprise the 24-

bit page and byte address sequence) and 4 don’t care bytes.

The

first 13 bits (PA12 - PA0) of the 23-bit address sequence specify which page of the main mem-

ory array to read, and the last 10 bits (BA9 - BA0) of the 23-bit address sequence specify the

starting byte address within the page. To perform a continuous read from the binary page size

(512 bytes), the opcode (E8H) must be clocked into the device followed by three address bytes

and 4 don’t care bytes. The first 13 bits (A21

- A9) of the 22-bits sequence specify which page of

the main memory array to read, and the last 9 bits (A8 - A0) of the 22-bits address sequence

specify the starting byte address within the page. The don’t care bytes that follow the address

bytes are needed to initialize the read operation. Following the don’t care bytes, additional cloc

k

pulses on the SCK pin will result in data being output on the SO (serial output) pin.

The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care

bytes,

and

the

reading

of

data.

When

the

end

of

a

page

in

main

memory

is

reached

during

a

Continuous Array Read, the device will continue reading at the beginning of the next page with

no delays incurred during the page boundary crossover (the crossover from the end of one page

to the beginning of the next page). When the last bit in the main memory array has been read,

the device will continue reading back at the beginning of the first page of memory. As with cross-

ing over page boundaries, no delays will be incurred when wrapping around from the end of the

array to the beginning of the array.

A low-to-high transition on the CS pin will terminate the read operation and tri-state the output

pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by

the fCAR1 specification. The Continuous Array Read bypasses both data buffers and leaves the

contents of the buffers unchanged.

6.1

连续阵列读取（传统命令：

E8H

）

：高达

66 MHz

通过提供一个初始的主存储器阵列的起始地址，连续阵列读

命令可以被用来顺序地读取从设备的连续的数据流

;

没有额外的寻址信息或控 制信号需要

被提供。数据闪存集成了一个内部地址计数器会自动

在每个时钟周期的增量，允许一个连续的读操作，而不需要

< /p>

额外的地址序列。要执行连续读的

DataFlash

大小（

528

字节）

，后跟三个地址的设备操作码的

E8H

必须移入

字节（其中包括

24

位的网页地址和字节序列）和

4

不在乎字节。该

第

13

位（

PA12 - PA0

）的< /p>

23

位地址序列指定页面的主要

MEM

ory

阵列读，最后

10

位（

BA9 - BA0

）的

23

位地址序列指定

起始字节地址内页。要执行连续读取二进制页大小

512

字节）

，操作码 （

E8H

）必须移入设备，然后通过三个地址字节

和

4

不在乎字节。的

22

位序列的第

13

位（

A21 - A9

）指定页

< /p>

主存储器阵列读，最后

9

位（

）的

22

位的地址序列

指定页面内的起始字节地址。不在乎字节后面的地址

字节需要初始化读操作。继不在乎字节，额外的时钟

SCK

引脚上的脉冲会导致数据上的

SO

（串行输出）引脚输出。

CS

引脚必须保持低在加载过程中的操作码，地址字节，不关心

字节，而数据的读出。当在主存储器中的页面的结束达到阵列读期间

aCont inuous

，该设备

将继续读取下一个页面的开始与

没有在页面边界交叉（交叉从一个页面的结束产生延误

下页的开头）

。当主存储器阵列中的最后一位被读取，

该设备将继续读取在存储器的第一页的开头。由于与交叉

ING

在页边界时将产生环绕着结束的，没有延迟

< br>

数组的数组的开始。

从低到 高的

CS

引脚上的过渡将终止读操作和三态输出

引脚（

SO

）

。最高

SCK

频率连续阵列读允许定义

的

fCAR1

规范。连续 阵列读绕过这两个数据缓冲区和叶

内容缓冲器不变。

6.2 Continuous Array Read (High Frequency Mode: 0BH): Up to 66 MHz

This command can be used with the serial interface to read the main memory array sequentially

in high speed mode for any clock frequency up to the maximum specified by fCAR1. To perform

a

continuous read array with the page size set to 528 bytes, the CS must first be asserted then an

opcode 0BH must be clocked into the device followed by three address bytes and a dummy

byte. The first 13 bits (PA12 - PA0) of the 23-bit address sequence specify which page of the

main memory array to read, and the last 10 bits (BA9 - BA0) of the 23-bit address sequence

specify the starting byte address within the page. To perform a continuous read with the page

size set to 512 bytes, the opcode, 0BH, must be clocked into the device followed by three

address bytes (A21 - A0) and a dummy byte. Following the dummy byte, additional clock pulses

on the SCK pin will result in data being output on the SO (serial output) pin.

The CS pin must remain low during the loading of the opcode, the address bytes, and the read-

ing of data. When the end of a page in the main memory is reached during a Continuous Array

Read, the device will continue reading at the beginning of the next page with no delays incurred

during the page boundary crossover (the crossover from the end of one page to the beginning of

the next page). When the last bit in the main memory array has been read, the device will con-

tinue reading back at the beginning of the first page of memory. As with crossing over page

boundaries, no delays will be incurred when wrapping around from the end of the array to the

beginning of the array. A low-to-high transition on the CS pin will terminate the read operation

and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous

Array Read is defined by the fCAR1 specification. The Continuous Array Read bypasses both

data buffers and leaves the contents of the buffers unchanged.

6.2

连续阵列读（高频模式：

0BH

）

：高达

6 6 MHz

此命令可用于串行接口读取主存储器阵列顺序

< /p>

在高速模式下最大由

fCAR1

指定任何 时钟频率高达。要执行

连续读取阵列的页面大小设置为

528

字节时，

CS

必须首先被断言然后

操作码

0BH< /p>

必须移入三个地址字节和一个虚拟的设备

字节。

23

位地址序列的第

13

位（

PA12 - PA0

）指定的哪一页

主存储器阵列 读，和最后一个

10

位的

23

位的地址序列（

BA9 - BA0

）

指定页面内的起始字节地址。要执行连续读取页面

512

字节，操作码，

0BH

必须移入设备，然后由三个

地址字节（

A21 - A0

）和一个空字节。虚拟字节，额外的时钟脉冲

SCK

引脚将导致数据上的

SO

（串行输出）引脚输出。

C S

引脚必须保持低的加载过程中的操作码，地址字节，读

ing

的数据。当在主内存中的页面年底时达到连续阵列