海大-EDA实验1参考答案

Laboratory Exercise 1

Switches, Lights, and Multiplexers

ED

实验参与答案

Part1

library ieee;

use _logic_;

entity part1 is

port(SW

:in

std_logic_vector(17 downto 0);

LEDR

:out

std_logic_vector(17 downto 0));

end part1;

architecture Behavior of part1 is

begin

LEDR <= SW;

end Behavior;

part2

library ieee;

use _logic_;

--

a 2 to 1 multiplexer entity

entity mux21 is

port(in_x, in_y, in_s

:

in

std_logic;

out_m

:out

std_logic);

end mux21;

--

a 2 to 1 multiplexer architecture

architecture structural of mux21 is

signal u, v

:

std_logic;

begin

u <= in_x and (not in_s);

v <= in_y and in_s ;

out_m <= u or v

end structural;

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--

a eight

-

bit wide 2 to 1 multiplexer

library ieee;

use _logic_;

--

eight< /p>

-

bit wide 2 to 1 multiplexer entity

entity mux21_8bit is

port(

SW

: in std_logic_vector (17 downto 0);

--

SW

:

in std_logic_vector (15 downto 8);

--

SW

:

in std_logic_vector (17 downto 17);

LEDR

: out std_logic_vector (7 downto 0));

end mux21_8bit;

- -

eight

-

bit wide 2 to 1 multiplexera rchitecture

architecture Structural of mux21_8bit is

component mux21

port(in_x, in_y, in_s

:

in

std_logic;

out_m

:out

std_logic);

end component;

begin

U1:

mux21

port map (in_x=>SW(0), in_y=>SW(8), in_s=>SW(17), out_m=>LEDR(0));

U2:

mux21

port map (in_x=>SW(1), in_y=>SW(9), in_s=>SW(17), out_m=>LEDR(1));

U3:

mux21

port

map

(in_x=>SW(2),

in_y=>SW(10),

in_s=>SW(17),

out_m=>LEDR(2));

U4:

mux21

port

map

(in_x=>SW(3),

in_y=>SW(11),

in_s=>SW(17),

out_m=>LEDR(3));

U5:

mux21

port

map

(in_x=>SW(4),

in_y=>SW(12),

in_s=>SW(17),

out_m=>LEDR(4));

U6:

mux21

port

map

(in_x=>SW(5),

in_y=>SW(13),

in_s=>SW(17),

out_m=>LEDR(5));

U7:

mux21

port

map

(in_x=>SW(6),

in_y=>SW(14),

in_s=>SW(17),

out_m=>LEDR(6));

U8:

mux21

port

map

(in_x=>SW(7),

in_y=>SW(15),

in_s=>SW(17),

out_m=>LEDR(7));

end Structural;

part3

library ieee;

use _logic_;

--

a 2 to 1 multiplexer entity

entity mux21 is

port(in_x, in_y, in_s

:

in

out_m

std_logic;

:out

std_logic);

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end mux21;

--

a 2 to 1 multiplexer architecture

architecture structural of mux21 is

signal signal_u, signal_v

:

std_logic;

begin

signal_u <= in_x and (not in_s);

signal_v <= in_y and in_s

out_m <= signal_u or signal_v ;

end structural;

library ieee;

use _logic_;

--

a 5 to 1 multiplexer entity

entity mux51 is

port(in5_u, in5_v, in5_w, in5_x, in5_y, in5_s1, in5_s2, in5_s0

:in

std_logic;

out5_m

:out

std_logic);

end mux51;

--

a 5 to 1 multiplexer architecture

architecture Structural of mux51 is

component mux21

port (in_x, in_y, in_s

:in

std_logic;

out_m

:out

std_logic);

end component;

signal signal_a, signal_b, signal_c

:

std_logic;

begin

U1:

mux21

port map (in_x=>in5_u, in_y=>in5_v, in_s=>in5_s0, out_m=>signal_a);

U2:

mux21

port map (in_x=>in5_w, in_y=>in5_x, in_s=>in5_s0, out_m=>signal_b);

U3:

mux21

port

map

(in_x=>signal_a,

in_y=>signal_b,

in_s=>in5_s1,

out_m=>signal_c);

U4:

mux21

port map (in_x=>signal_c, in_y=>in5_y, in_s=>in5_s2, out_m=>out5_m);

end Structural;

library ieee;

use _logic_;

--

a 3bit 5 to 1 multiplexer entity

entity mux51_3bit is

port(SW

: in

std_logic_vector (17 downto 0);

LEDR

: out

std_logic_vector (17 downto 0);

LEDG

: out

std_logic_vector (2 downto 0));

end mux51_3bit;

--

a 3bit 5 to 1 multiplexer architecture

architecture structural of mux51_3bit is

component mux51

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port(in5_u, in5_v, in5_w, in5_x, in5_y, in5_s1, in5_s2, in5_s0

:in

std_logic;

out5_m

:out

std_logic);

end component;

begin

LEDR <= sw;

U1:

mux51

port

map

(in5_u=>SW(0),

in5_v=>SW(3),

in5_w=>SW(6),

in5_x=>SW(9),

in5_y=>SW(12),

in5_s0=>SW(15),

in5_s1=>SW(16),

in5_s2=>SW(17),

out5_m=>LEDG(0));

U2:

mux51

port

map

(in5_u=>SW(1),

in5_v=>SW(4),

in5_w=>SW(7),

in5_x=>SW(10),

in5_y=>SW(13),

in5_s0=>SW(15),

in5_s1=>SW(16),

in5_s2=>SW(17),

out5_m=>LEDG(1));

U3:

mux51

port

map

(in5_u=>SW(2),

in5_v=>SW(5),

in5_w=>SW(8),

in5_x=>SW(11),

in5_y=>SW(14),

in5_s0=>SW(15),

in5_s1=>SW(16),

in5_s2=>SW(17),

out5_m=>LEDG(2));

end structural;

part4

library ieee;

use _logic_;

--

a 7

-

segment decoder entity

entity decoder is

port(decoder_in_3

:

in

std_logic_vector(2 downto 0);

HEX0

:

out

std_logic_vector(0 to 6));

end decoder;

--

a 7

-

segment decorder architecture

architecture behavioral of decoder is

begin

process(decoder_in_3)

begin

case decoder_in_3 is

when

=> HEX0

<=

when

=> HEX0 <=

when

=> HEX0 <=

when

=> HEX0 <=

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when others => Hex0 <=

end case;

end process;

end behavioral;

part5

library ieee;

use _logic_;

entity part5 is

port(

SW

: in

std_logic_vector(17 downto 0);

HEX0,HEX1,HEX2,HEX3,HEX4

: out

std_logic_vector(6 downto 0));

end part5;

architecture Behavior of part5 is

component mux51_seg7

port(Mux51_seg7_in

: in

std_logic_vector(17 downto 0);

Seg

: out

std_logic_vector(6 downto 0));

end component;

begin

U0:

mux51_seg7

port map(Mux51_seg7_in=>SW,Seg=>HEX0);

U1:

mux51_seg7

port

map(Mux51_seg7_in(17

downto

15)=>SW(17

downto

15),

Mux51_seg7_in(14 downto 12)=>SW(11 downto 9),

Mux51_seg7_in(11 downto 9)=>SW(8 downto 6), Mux51_seg7_in(8 downto 6)=>SW(5

downto 3),

Mux51_seg7_in(5

downto

3)=>SW(2

downto

0),

Mux51_seg7_in(2

downto

0)=>SW(14 downto 12),

Seg=>HEX1);

U2:

mux51_seg7

port

map(Mux51_seg7_in(17

downto

15)=>SW(17

downto

15),

Mux51_seg7_in(14 downto 12)=>SW(8 downto 6),

Mux51_seg7_in(11 downto 9)=>SW(5 downto 3), Mux51_seg7_in(8 downto 6)=>SW(2

downto 0),

Mux51_seg7_in(5

downto

3)=>SW(14

downto

12),

Mux51_seg7_in(2

downto

0)=>SW(11 downto 9),

Seg=>HEX2);

U3:

mux51_seg7

port

map(Mux51_seg7_in(17

downto

15)=>SW(17

downto

15),

Mux51_seg7_in(14 downto 12)=>SW(5 downto 3),

Mux51_seg7_in(11 downto 9)=>SW(2 downto 0), Mux51_seg7_in(8 downto 6)=>SW(14

downto 12),

Mux51_seg7_in(5

downto

3)=>SW(11

downto

9),

Mux51_seg7_in(2

downto

0)=>SW(8 downto 6),

Seg=>HEX3);

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U4:

mux51_seg7

port

map(Mux51_seg7_in(17

downto

15)=>SW(17

downto

15),

Mux51_seg7_in(14 downto 12)=>SW(2 downto 0),

Mux51_seg7_in(11

downto

9)=>SW(14

downto

12),

Mux51_seg7_in(8

downto

6)=>SW(11 downto 9),

Mux51_seg7_in(5

downto

3)=>SW(8

downto

6),

Mux51_seg7_in(2

downto

0)=>SW(5 downto 3),

Seg=>HEX4);

end Behavior;

----------------------------------------- -------------------------------------------------- ----

-----------

A circuit that can select and display one of five characters

------------------------

------------------------------------------- -------------------------------------------------- --

library ieee;

use _logic_;

entity mux51_seg7 is

port(Mux51_seg7_in

: in

std_logic_vector(17 downto 0);

Seg

: out

std_logic_vector(6 downto 0));

end mux51_seg7;

architecture Behavior of mux51_seg7 is

component mux51_3bit

port(S, U, V, W, X, Y

: in

std_logic_vector(2 downto 0);

M

: out

std_logic_vector(2 downto 0));

end component;

component char_7seg

port(C

: in

std_logic_vector(2 downto 0);

Display

: out

std_logic_vector(6 downto 0));

end component;

signal M : std_logic_vector(2 downto 0);

begin

M0: mux51_3bit

port

map(Mux51_seg7_in(17

downto

15),

Mux51_seg7_in(14

downto

12),Mux51_seg7_in(11 downto 9),

Mux51_seg7_in(8

downto

6),Mux51_seg7_in(5

downto

3),Mux51_seg7_in(2

downto

0),M);

H0: char_7seg

port map(M, Seg);

end Behavior;

----------------------------------------- -------------------------------------------------- ----

------------------------------

a 3bit mux51

-------------------- ---------------------------------

----- -------------------------------------------------- ----------------------------------------

library ieee;

use _logic_;

--

a 2 to 1 multiplexer entity

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