vcs常用命令

SYNOPSYS VCS

常用命令使用详解

(2013-01-18 09:28:08)

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杂谈

VCS

对

verilog

模型进行仿真包括两个步骤：

1.

编译

verilog

文件成为一个可执行的二进制文 件命令为：

vcs source_files

2.

运行该可执行文件：

./simv

类似于

NC,

也有单命令行的方式：

vcs source_files -R

-R

命令表示

,

编译后立即执行。

vcs

常用的命令选项如下：

-cm line|cond|fsm|tgl|obc|path

设定

coverage

的方式

+define+macro=value+

预编译宏定义

-f filename

RTL

文件列表

+incdir+directory+

添加

include

文件夹

-I

进入交互界面

-l

logfile

文件名

-P

定义

PLI

的列表

(Tab)

文件

+v2k

使用推荐的标准

-y

定义

verilog

的库

-notice

显示详尽的诊断信息

-o

指定 输出的可执行文件的名字

,

缺省是

si mv

+ nospecify

不对

SPECIFY

模块进行时序检查和路径

延时计算

+ notimingcheck

不进 行时序检查；但是还是把

path

延时

加入仿真中

Summary of vcs compile options:

-ASFLAGS

-B

generate long call instructions in native assembly

code (HP only)

-CC

-CFLAGS

-LDFLAGS

-I

enable interactive/postprocessing debugging

capabilities

-ID

get host identification information

-M

enable incremental compilation (see manual)

-Mupdate

enable incremental compilation and keep the Makefile

up- to-date

-Marchive[=N]

create intermediate libs to reduce link line length;

N objs per lib

-P

plitab

compiles

user-defined

pli

definition

table

'plitab'

-PP

enable optimizer postprocessing capabilities for

vcd+

-R

after compilation, run simulation executable

-RI

after compilation, run simulation under xvcs

(Implies -I)

-RIG

run simulation under xvcs without compiling

(executable has to exist)

-RPP

run xvcs in postprocessing mode (requires file

created by vcdpluson)

-V[t]

verbose mode; with 't', include time information

-as

foo use foo as the assembler

-cc

foo use foo as the C compiler

-cpp

foo use foo as the C++ compiler

-e

specify

the

name

of

your

main()

routine.

(see

manual

section

7-11

for more details).

-f file

reads 'file' for other options

-gen_c

generate C code (for HP and Sun, default is

-gen_obj)

-gen_asm

generate native assembly code (HP and Sun only)

-gen_obj

generate native object code (HP and Sun only)

-ld

foo

use

foo

as

the

linker.

(refer

vcs

manual

for

compatibility with -cpp option)

-line

enable

single-stepping/breakpoints

for

source

level debugging

-lmc-swift

include lmc swift interface

-lmc-hm

include lmc hardware modeler interface

-vera

add VERA 4.5+ libraries

-vera_dbind

add VERA 4.5+ libraries for dynamic binding

-location

display full pathname to vcs installation for

this platform.

-vhdlobj

generate a vhdl obj for simulating in a vhdl design

-mixedhdl

include MixedHDL-1.0 interface