VCS后缀选项说明

编译

verilog

文件成为一个可执行的二进 制文件命令为

:

$$> vcs source_files

2.

运行该可执行文件

$$> ./simv

类似于

NC,

也有单命令行的方式

:

$$> vcs source_files -R

-R

命令表示

,

编译后立即执行

.

下面讲述常用的命令选项

:

-cm line|cond|fsm|tgl|obc|path

设定

coverage

的方式

+define+macro=value+

预编译宏定义

-f filename

RTL

文件列表

+incdir+directory+

添加

include

文件夹

-I

进入交互界面

-l

logfile

文件名

-P

< br>定义

PLI

的列表

(T

ab)

文件

+v2k

使用推荐的标准

-y

定义

verilog

的库

-notice

显示详尽的诊断信息

-o

< br>指定输出的可执行文件的名字

,

缺省是

< br>sim.v

zz 51life

?

Summary of vcs compile options:

-------------------------------

-ASFLAGS

pass 'opts' to the assembler

-B

generate long call instructions in native assembly code

(HP only)

-CC

pass 'opts' to C compiler

-CFLAGS

pass 'opts' to C compiler

-LDFLAGS

pass 'opts' to C compiler on load line only

-I

enable interactive/postprocessing debugging capabilities

-ID

get host identification information

-M

enable incremental compilation (see manual)

-Mupdate

enable incremental compilation and keep the Makefile

up-to-date

-Marchive[=N]

create intermediate libs to reduce link line length; N

objs per lib

-P plitab

compiles user-defined pli definition table 'plitab'

-PP

enable optimizer postprocessing capabilities for vcd+

-R

after compilation, run simulation executable

-RI

after compilation, run simulation under xvcs (Implies -I)

-RIG

run simulation under xvcs without compiling (executable

has to exist)

-RPP

run xvcs in postprocessing mode (requires file created

by vcdpluson)

-V[t]

verbose mode; with 't', include time information

-as foo

use foo as the assembler

-cc foo

use foo as the C compiler

-cpp foo

use foo as the C++ compiler

-e

specify the name of your main() routine.

(see manual section 7-11 for more details).

-f file

reads 'file' for other options

-gen_c

generate C code (for HP and Sun, default is -gen_obj)

-gen_asm

generate native assembly code (HP and Sun only)

-gen_obj

generate native object code (HP and Sun only)

-ld foo

use foo as the linker. (refer vcs manual for compatibility

with -cpp option)

-line

enable single-stepping/breakpoints for source level

debugging

-lmc-swift

include lmc swift interface

-lmc-hm

include lmc hardware modeler interface

-vera

add VERA 4.5+ libraries

-vera_dbind

add VERA 4.5+ libraries for dynamic binding

-location

display full pathname to vcs installation for this platform

-vhdlobj

generate a vhdl obj for simulating in a vhdl design

-mixedhdl

include MixedHDL-1.0 interface

-mhdl

include MixedHDL-2.0 interface and library

-q

quiet mode

-platform

display name of vcs installation subdirectory for this

platform

-syslib 'libs'

specify system libraries (placed last on the link line) eg

-lm

-o exec

name the executable simulation model 'exec' (default is

'simv')

-u

treat all non text string characters as uppercase

-v file

search for unresolved module references in 'file'

-y libdir

search for unresolved module references in directory

'libdir'

+acc

enable pli applications to use acc routines (see manual)

+ad

include anlog simulation interface and library

+adfmi=

ADFMI support for vcs-ace

+cliedit

enable command line edit/recall (see doc/)

+cli

enable command line interactive debugging (see manual)

+cmod

Enabling cmodule feature

+cmodext+cmodext

Changing cmodule extension to cmodext

+cmodincdir+cmoddir

Cmodule Include directory

+cmoddefine+macro

define cmodule source 'macro' in the form of

XX=YY

+define+macro

define hdl source 'macro' to have value

+plusarg_save

hardwire the plusargs, which follow this flag, into

simv

+plusarg_ignore

turn off +plusarg_save

+prof

tells vcs to profile the the design and generate

file

+race

tells vcs to generate a report of all race conditions during

simulation

and write this report in the file

+rad+1

enable level 1 radiant optimizations (See Release Notes)

+rad+2

enable level 2 radiant optimizations (See Release Notes)

+libext+lext

use extension 'lext' when searching library directorys

+librescan

search from beginning of library list for all undefined

mods

+incdir+idir

for `include files, search directory 'idir'

+nospecify

suppress path delays and timing checks

+notimingchecks

suppress timing checks

+optconfigfile+foo use 'foo' as the optimization config file (See Release

Notes)

+vcsd

enable the VCS Direct sim kernel interface

-cmhelp

enable CoverMeter help. CoverMeter should be

installed

and environment variable CM_HOME should be set.

-cm

enable VCS to first run cmSource to instrument the

Verilog source files on the command line, and then to

compile the instrumented source files

-cm_all

enable VCS to link CoverMeter into the VCS executable

in a way that enables line, condition, and FSM coverage

and establishes the direct link. Enabling all types of coverage

and the

direct link is the default condition when you

include the -cm option so

you can omit this option

-cm_lineonly

enable VCS to link CoverMeter into the VCS

executable in a way that only enables line coverage when it

also establishes the direct link. Use this option for faster simulation and

when you only need line coverage

Compile-Time

Options

********************

-f

Specifies

a

file

that

contains

a

list

of

pathnames

to

source

files

and

compile-time

options.

-F

Same

as

the

-f

option

but

allows

you

to

specify

a

path

to

the

file

and

the

source

files

listed

in

the

file

do

not

have

to

be

absolute

pathnames.

-h

Displays

a

succinct

description

of

the

most

commonly

used

compile-time

and

runtime

options.

-l

(lower

case

L)

Specifies

a

log

file

where

VCS

records

compilation

messages

and

runtime

messages

if

you

include

the

-R,

-RI,

or

-RIG

options.

-line

Enables

stepping

through

the

code

and

source

line

breakpoints

in

VirSim.

-M

Enables

incremental

compilation,

but

do

not

overwrite

the

makefile.

-Mupdate

Enable

incremental

compilation

and

overwrite

the

make

file.

-notice

Enables

verbose

diagnostic

messages.

-o

Specifies

the

name

of

the

executable

file

that

is

the

product

of

compilation.

The

default

name

is

simv

(

on

Windows).

-ova_cov

Enables

functional

coverage.

-P

<>

Specifies

a

PLI

table

file.

-R

Run

the

executable

file

immediately

after

VCS

links

together

the

executable

file.

You

can

add

any

runtime

option

to

the

vcs

command

line.

-s

Stop

simulation

just

as

it

begins.

Use

this

option

with

the

-R

and

+cli

options.

-timescale=/

If

only

some

source

files

contain

the

`timescale

compiler

directive

and

the

ones

that

don't

appear

first

on

the

vcs

command

line,

use

this

option

to

specify

the

time

scale

for

these

source

files.

-V

Enables

the

verbose

mode.

-v

Specifies

a

Verilog

library

file

to

search

for

module

definitions.

-vera

Specifies

the

standard

VERA

PLI

table

file

and

object

library.

-y

Specifies

a

Verilog

library

directory

to

search

for

module

definitions.

+2state

Enables

2

state

simulation.

+cli+[=]1|2|3|4

Enable

CLI

debugging.

1

enables

you

to

see

the

values

of

nets

and

registers

and

deposit

values

to

registers.

2

also

enables

breakpoints

on

value

changes

of

nets

and

registers.

3

also

enables

you

to

force

a

value

on

nets.

4

also

enables

you

to

force

a

value

on

a

register.

You

can

specify

a

module

to

enable

CLI

debugging

only

for

instances

of

the

module.

+define+=

Defines

a

text

macro.

Test

for

this

definition

in

your

Verilog

source

code

using

the

`ifdef

compiler

directive.

+incdir+

Specifies

the

directories

that

contain

the

files

you

specified

with

the

`include

compiler

directive.

You

can

specify

more

that

one

directory,

separating

each

path

name

with

the

+

character.

+libext+

Specifies

that

VCS

only

search

the

source

files

in

a

Verilog

library

directory

with

the

specified

extension.

You

can

specify

more

than

one

extension,

separating

each

extension

with

the

+

character.

For

example,

+libext++.v

specifies

searches

library

files

with

no

extension

and

library

files

with

the

.v

extension.

Enter

this

option

when

you

enter

the

-y

option.

+maxdelays

Use

maximum

value

when

min:typ:max

values

are

encountered

in

delay

specifications

SDF

files.

+mindelays

Use

minimum

value

when

min:typ:max

values

are

encountered

in

delay

specifications

and

SDF

files.

+notimingcheck

Suppresses

timing

checks

in

specify

blocks.

+plusarg_ignore

Also

enter

this

option

in

the

file

that

you

specify

with

the

-f

option

so

that

VCS

does

not

pass

to

the

simv

executable

or

to

VirSim

the

options

that

follow

in

the

file.

Use

this

option

with

the

+plusarg_save

option

to

specify

that

other

options

should

not

be

passed.