LVDS, CML, ECL differential interfaces

LVDS, CML, ECL-differential interfaces with odd

voltages

By John Goldie, Applications Manager

There are m

any differential signaling technologies available today. Som

e are

defined by industry standard committees, such as the TIA, IEEE, or JEDEC groups.

Others are more

ay have unique electrical

characteristics all their own. Both types were developed for different reasons, some

focus on ultra speed such as ECL and CML, while others focused on two or m

ore

attributes. LVDS for example, focused on both high-speed and low-power operation.

Here is what you should know about som

e of today's popular high- speed differential

interface technologies.

The

three popular high-speed differential interface technologies discussed are:LVDS

- Low Voltage Differential Signaling, ECL - Em

itter Coupled Logic, and PECL /

LVPECL options CML - Current Mode Logic.

There are som

e additional variants of each of these, however they tend to be

application specific or less common and are therefore beyond the scope of this

article. There are also m

any other interface technologies that are not differential,

thus they tend not to support high-speed (>

1Gbps) operation and are typically

limited by their small noise m

argins. Examples of these are standard logic swings

(LVCMOS), HSTL, BTL, and GTL. An overview of these can be found in National's

Applications Note #1123

titled

Three for Speed: EC

L - LVDS - CML

ECL - Em

itter Coupled Logic - is the oldest of the three and dates back to the early

1960s. Motorola pioneered ECL with its MECL (Motorola ECL) family. Since then ECL

has evolved into m

any enhanced fam

ilies. These include the 10k, 100k, ECLinPS,

and even som

e m

ore recent flavours such as RSECL for Reduced Swing ECL, which

features an LVDS-like 400mV, output swing. Fairchild, also an ECL pioneer brought

out the

first sub-nano second ECL parts in the early 1970s. The 100k family brought

the critical feature of supply voltage and tem

perature com

pensation, providing a

very stable output. ECL can be used single-endedly or differentially depending upon

the application and noise margins needed. The drivers are low impedance open

emitter outputs that generate a typical 700 to 800 m

V output voltage. The output

stage is operated in the active region, saturation is prevented, thus ECL's fam

ous

fast and balanced edge rates are obtained. The output is typically terminated with

50 Ohms to a term

ination rail that is two volts less than the m

ore positive rail. ECL

parts are commonly powered between ground and -5.2V. Due to the negative rail

requirement and compatibility with other popular devices (logic, ASICs,

?

Ps...), the

positive rail operation of ECL was prom

oted. PECL - Positive Emitter Coupled Logic,

also som

etime referred to as Pseudo ECL is really just operating the ECL devices

between and positive voltage and ground, vs ground and a negative voltage.

LVPECL - Low Voltage PECL - is

the

term

used to describe PECL that is powered from

a 3.3V power supply. There are even other versions available today that support

operation from

rails less than 3.3V.

ECL has been m

ore of a defacto standard with m

ajor vendors providing different

fam

ilies. Within a few standards, ECL has been standardized as the physical layer.

This includes the TIA's

ANSI/TIA/EIA-612

at Data Signaling Rates to 52 Mbit/s

receiver input characteristics of 100k ECL. The '612 standard maybe used with the

ANSI/TIA/EIA-613

standard

inal

Equipment and Data Circuit Terminating Equipment

echanical

and functional requirem

ents the HSSI interface. HSSI was developed by Cisco

System

s and T3plus Networks and later standardized by the TIA.

ECL has also been standardized by ANSI in the HIPPI (High-Performance Parallel

Interface) standards. The HIPPI standards are also com

plete standards defining all

electrical, m

echanical and functional parameters for various HIPPI applications. The

TIA/EIA-612 standard is unique in that it partitions the electrical portion in its own

standard allowing it to be referenced by other applications or standards.

Key points on ECL, are its fast and balanced output edges, a low output impedance,

high drive capability, and differential or single-ended operation. Limit

ing factors of

ECL have been the negative rails, com

patibility with other devices, the need for the

terminating rail (VTT), and typically higher power dissipation.

Several bus configurations are shown in figure 1 for ECL.

Figure 1:

A: ECL terminated in 50 Ohms to VTT; B: PECL terminated by Thevenin

network, R1/R2 = 50 Ohms; C: Differential ECL terminated by 100 Ohm

parallel

termination;

D: Differential ECL Multipoint bus terminated by 50 Ohms to VTT at each end of the

bus.

Figure 1A shows a common point-to-point application with a 50 Ohm termination to

the VTT rail. Figure 1B is the sam

e application but is PECL and uses a Thevenin

termination to generate the VTT, with the penalty of increased power dissipation

(8X). If only a few lines are required in the application this is typically the preferred

implem

entation. If m

any lines are required, it is typically better to employ a

dedicated VTT rail for termination purposes. If mixing PECL and CMOS devices, two

separate power planes are recommended. Figure 1C shows the common differential

point-to-point interconnection for ECL. Since a 100-Ohm

parallel termination is

used, pull downs at the driver are required. Figure 1D shows a m

ultipoint ECL

backplane application.

LVDS

- Low Voltage Differential Signaling - dates back to the early 1990s and was

pioneered by National Semiconduc

tor. National directly helped standardize LVDS at

that tim

e being the editor of both the IEEE and TIA projects. LVDS is standardized

as an electrical layer standard by the TIA and is published as

ANSI/TIA/EIA-644-A

.

An IEEE project at that tim

e was working on a standard known as SCI, which

originally specified an ECL interface. An addendum was added that specified a lower

swing, lower power alternative to ECL, which was the IEEE version of LVDS (a.k.a.

IEEE 1596.3). Due to its vertical application, the generic TIA version of LVDS is

more common today. In fact it has been specified as the physical layer in m

any

applications ranging from

flat panel notebook displays to fram

e grabbers to optical

transceivers and many others.

National developed and offered m

any industry firsts in LVDS which included FPD

Link, Channel-Link, Military grade LVDS and even the first stand-alone line driver /

receiver standard products.

LVDS is a high-speed and low-power differential interface for generic applications. It

supports both point-to-point and also m

ultidrop bus configurations as shown in

figure 2. This flexibility m

akes it very versatile. The driver provides a typic

al 350mV

differential output voltage centered at about +1.25V. The receiver is specified with

a 100mV threshold over the receiver's input range of ground to +

2.4V. This allows

for the nominal active signal to shift up or down 1V in common-

m

ode due to ground

potential differences or coupled noise. The driver is intended to be used with

100-Ohm interconnects term

inated in 100-Ohms. Data rate is device and

application specific but it tends to be in the DC to 2.5Gbps range. Power is

minimized in three ways. The load current is limited to 3.5mA, the current m

ode

driver tends to limit dynamic power dissipation, and stati

c current is minimized by

the use of sub-m

icron CMOS processes. LVDS is unique in that it delivers high-speed

operation while consuming little power.

Figure 2:

A: LVDS terminated by 100 Ohm parallel termination; B: Multidrop LVDS

terminated by 100 Ohm parallel termination at the far end only, stubs off the m

ain

line (1) should be minimized in length.

A newer related LVDS standard is the

ANSI/TIA/EIA-899

standard known as

M-LVDS. This version supports a multipoint bus with double terminations. Due to

the bus configuration and stub lengths, M-LVDS is limited to 500 Mbps or less. A

multipoint M-LVDS bus is shown in figure 3. There are several other vendor specific

flavors of LVDS, such as National's BLVDS. Details on these flavours can be found in

the

National Edge

titled

Figure 3:

Multipoint LVDS bus terminated by two parallel terminations which are

equal to 100 Ohms or the effective loaded impedance of

the bus -

typically in the 54

to 100 Ohm range.

LVDS and M-LVDS provide true odd mode transmission and equal and opposite

currents flow within the pair. This and the sm

all output current (3.5mA) tends to

make LVDS low in EMI. LVDS is a very versatile technology, and supports a variety

of bus configurations.

CML

- Current Mode Logic - The origins of CML are m

ore difficult to track. CML tends

to be m

ainly a vendor implementation with less official standardization. This makes

its roots m

ore difficult to track. Som

e state that it predates ECL with origins at

General Electric, others note that it grew out of I2L, (Injection Current Logic), or

CCSL (Compatible Current-sinking logic) in the 1980s. Still others state som

e work

in the early 1990s as its source. Many others see it as sim

ply upside-down ECL.

Today CML has becom

e very popular due to its sim

plicity and speed especially for

multi-gigabit SerDes applications.

CML is a high-speed point-to-point interface as shown in figure 4. A unique feature

of CML is that it typically does not require any external resistors as termination is

provided internally by both the driver and the receiver devices. CML supports data

rates above 10 Gbps depending upon the process for the drivers and receivers. CML

maybe DC coupled or AC coupled if encoding is used. CML uses a passive pull up to

the supply rail, which is typically 50 Ohms. CML tends to be vendor specific, so a

careful review of datasheets is recommended to determ

ine inter-operation

especially in DC coupled applications.

Figure 4:

A: Point-to-Point CML with internal source and load terminations - 50

Ohm pull ups to the positive rail; B: AC coupled Point

-to-Point CML with internal

source and load terminations - driver and receiver may be powered from different

rails.