-
(4)
SPI Digital Timing Diagram
In SPI Mode (
SPI_SE =
1
), the 3-wire SPI interface is used to
configure the frequency as well as
internal registers. Series data
sequence of 3-wire
SPI is shown in
following Figure. This
25-bit
data
stream consists of
4 address
bits
, 1 read/write control bit and 20
data bits. Data transfer is
LSB first.
During
write
cycle
(R/W
=
1),
the
chip
will
sample
the
SPIDATA
on
the
rising
edge
of
SPICLK
.
Sampled data will be temporally stored
in internal shift register. One the rising edge of
SPILE
, data in
shift register will be latched into
specific register according to the address.
During
read
cycle
(R/W
=
0),
address
and
read/write
control
bit
are
sampled
at
rising
edge
of
SPICLK
, but
the data bits are sent at the falling edge of
SPICLK
.
LSB
1st data
MSB
2nd data
Invalid Data
SPILE
SPIDATA
A0
A1
A2
A3
R/W
D0
D1
D18
D19
SPICLK
t 1
t 2
t 3
t 6
t 7
t
t 4 t 5
Figure
6.1 Series data sequence on SPI interface
Unit
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
Typ.
Max.
t1
20
-
-
t2
20
-
-
t3
30
-
-
t4
30
-
-
t5
100
-
-
t6
20
-
-
t7
100
-
-
Note:
1.) On the rising edge
of the SPICLK, one bit of data is transferred into
the shift register.
2.) SPILE should be
“L” when the data is transferred into
the shift register.
Channel
Selection Table
When pin 7 (SPI_SE) is set
at low voltage, the chip works as in the easy
channel selection mode and
the
pins
4(SPIDATA/CS0),
5(SPILE/CS1),
6(SPICLK/CS2)<
/p>
，
48(S)
and
8(BX)
are
used
for
channel
selection. Channel frequencies refer to
below table.
SPI_SE
Band
BX
S
0
1
X
X
5GHz
Band
0
0
0
1
A
B
E
SPI
0
0
1
X
000
5865M
5733M
5705M
001
5845M
5752M
5685M
010
5825M
CS[2:0]
011
100
101
110
111
5805M
5785M
5765M
5745M
5725M
5771M
5790M
5809M
5828M
5847M
5866M
5665M
5645M
5885M
5905M
5925M
5945M
three wire SPI
control pins
SPI mode
When pin 7 (SPI_SE) is set
at high (3.3V), the chip works as in the SPI mode
and the pins
4(SPIDATA/CS0),
5(SPILE/CS1) and 6(SPICLK/CS2) are used for
?SPI? inputs for 3
-wire
programming
Address 0x00: Synthesizer Register A
Bits
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
5G Default
0
0
－
0
0
0
0
0
0
0
0
SYN_RF_R_REG [14:0]
0
0
0
0
0
0
1
0
0
0
SYN_RF_R_REG [14:0]:
Default
5.8GHz: 0010H
R-counter
divider ratio control for RF Synthesizer.
For 5.8GHz
Default: 0
0008H
Crystal clock
(F
osc
)=: 8MHz
Reference clock=crystal
clock/R-counter=8MHz/8=1MHz
Address 0x01:
Synthesizer Register B
11
10
9
8
7
6
5
4
2
0
Bits
19
18
17
16
15
14
13
12
3
1
Name
5G Default
0
0
0
0
SYN_RF_N_REG
[12:0]
0
0
1
0
0
0
SYN_RF_A_REG [6:0]
0
0
1
0
1
0
0
1
0
1
Default
5.8GHz: 02A05H
Synthesizer counter default setting (
5.8Ghz band:5865MHz)
For 5.8Ghz band,
F
LO
=
2*(N*32+A)*(F
osc
/R)
Example: default
F
RF
=5865MHz, F
LO<
/p>
=5865-479=5386MH
z,
F
osc
=8MHz,
R=8
5385/2=(N*32+A)*8Mhz/8=2*(N*32+A)*1MHz
N=84(=1010100), A5(=0101)
For 5.8GHz default:
02A05H
SYN_RF_N_REG [12:0]:
N counter divider ratio control for RF
Synthesizer.
SYN_RF_A_REG
[6:0]:
A counter divider
ratio control for RF Synthesizer.
Address 0x02: Synthesizer Register C