Tanner Pro集成电路设计(CMOS倒相器的版图)

课程名称

Course

组件

NMOS

：

集成电路设计技术

项目名称

Item

CMOS

倒相器的版图设计与仿真

< /p>

组件

PMOS

：

组件< /p>

CONTACTP

：

组件

CONTACTN

：

CMOS

倒相器：

*.s pc

文件

(

瞬时分析

< br>):

* Circuit Extracted by Tanner Research's L-Edit V7.12 / Extract V4.00

* TDB File: H:cmoscmos, Cell: Cell0

* Extract Definition File: C:Program FilesTanner

* Extract Date and Time: 06/29/2011 - 00:18

.include H:ml2_

VPower VDD GND 5

va A GND PULSE (0 5 0 1n 1n 50n 100n)

.tran 1n 400n

.print tran v(A) v(F)

* WARNING: Layers with Unassigned AREA Capacitance.

*

*

*

*

*

*

* WARNING: Layers with Unassigned FRINGE Capacitance.

*

*

*

*

*

*

*

*

* WARNING: Layers with Zero Resistance.

*

*

*

*

* NODE NAME ALIASES

* 1 = VDD (21.5,66)

* 2 = F (32,36)

* 3 = A (18,35.5)

* 4 = GND (18.5,6)

M1 F A VDD VDD PMOS L=2u W=10u AD=55p PD=31u AS=55p PS=31u

* M1 DRAIN GATE SOURCE BULK (29 47 31 57)

M2 F A GND GND NMOS L=2u W=5u AD=27.5p PD=21u AS=27.5p PS=21u

* M2 DRAIN GATE SOURCE BULK (29 10 31 15)

* Total Nodes: 4

* Total Elements: 2

* Extract Elapsed Time: 1 seconds

.END

瞬时分析仿真波形图：

*.s pc

文件

(

直流分析

< br>):

* Circuit Extracted by Tanner Research's L-Edit V7.12 / Extract V4.00

* TDB File: H:cmoscmos, Cell: Cell0

* Extract Definition File: C:Program FilesTanner

* Extract Date and Time: 06/29/2011 - 00:18

.include H:ml2_

VPower VDD GND 5

va A GND 1

.dc va 0 5 0.02

.print dc v(F)