MIPS体系结构

OS

会将进程

B

的

ASID

或

PID

填入

ASID

寄存器中。

请记住：

对

TLB

的访问，

(ASID

+ VPN)

才是

Primary Key.

由于

MIPS

的

CACHE

属性是

Virtual ly Indexed, Physically tagged.

所以，任何地址的访 问，

CPU

都会

issue the request to MMU for TLB translation to get

the correct physical address, which then will be used for level cache matching.

与此同时 ，

CPU

会把虚拟地址信号传给

Lev el 1 Cache

控制器。然后，我们必须等待

MMU< /p>

的

Physical Address

数据。只有

physical tag

也

匹配上了，我们才能说一个：

Cache Hit.

所以，我们不需要担心不同的进程有相同的虚拟地址的事情。

弟兄们可以重温一下我们讲过的

Direct Mapped; Full Associative, and Set Associative.

从而理解为什么

Cache

中可以存在多个具有相同虚拟地址的

entry. For example,the above

Addr1 for proccess A and Addr1 for process B.

MIPS

异常和中断处理

(Exception and Interrupt handling)

任何一个

CPU

都要提供一个详细的异常和中断处理机制。一个软件系统，< /p>

如操作系统，

就是一个

时序逻辑系统，通 过时钟，

外部事件来驱动整个预先定义好的逻辑行为。

这也是为 什么当写一个

操作系统时如何定义时间的计算是非常重要的原因。

大家都非常清楚

UNIX

提供了一整套系统调用

(System

C all)

。系统调用其实就是一段

EXCEPTION

处理程序。

我们 可能要问：为什么

CPU

要提供

Exc petion

和

Interrupt Handling

呢？

*

处理

illegal behavior,

例如，

TLB Fault, or, we say, the Page fault; Cache Error;

* Provide an approach

for

accessing priviledged

resources, for e

xample, CP0 registers.

As we know, for user level tasks/processes, they are running

with the User Mode priviledge and are prohibilited to directly control CPO. CPU need

provide a mechanism for

them

to trap to kernel mode and

then

safely manipulate resources

that are only available

when CPU runs in kernel mode.

*

Provide

handling

for

external/internal

interrupts.

For

instance,

the

timer

interrupts

and watch dog exceptions. Those two interrupt/exceptions are very important for an

embedded system applicances.

Now let's get back to how MIPS supports its exception and interrupt handling.

For simplicty, all information below will be based on R7K CPU, which is derived from

the R4k family.

* The first thing for understanding MIPS exception handling is: MI

PS adopts **Precise

Exceptions**

mechanisms.

What

that

means?

Here

is

the

explaination

from

the

book

of

MIPS Run

instruction(the exception victim). All instructions preceding the exception victim in

execution

sequence are complete; any work done on the victim and on any subsequent instructions

(BNN NOTE: pipeline effects) has no side effects that the software need worry about.

The software that handles exceptions can ignore all the timing effects of the CPU's

implementations

上 面的意思其实很简单：

在发生

EXCEPTION

之前的一切计算行为会

**FINISH**

。

在发生

EXCEPTION

之后的一切计算 行为将不需考虑。

对绝大多数情况而言，如你要写一个系统调用

(System Call),

你只要记住：

MIP S

已经把

syscall

这条指令的地 址压在了

EPC

寄存器里。换句话说，在

MIPS

里，

compard

to

the PowerPC CPU srr1 register,

你需要

**explicitely**

refill the EPC register by EPC<-----EPC+4, before you use the eret

中断返回。只有这

样，你才能从系统调用中正确返回。

异常

/

中断 向量

(Exception/Interrupt Vector)

MIPS

的

Exception/Interrupt Vector

的

organizaion is not as good as PowerPC CPUs.

For PPC, every detailed exception cause is directed to a unqiue vector address.

MIPS

is otherwise. Below is a recap of MIPS exception/interrupt vectors.

(We herein only talk about running MIPS CPU in the 32 bit mode )

Reset, NMI 0x8000 0000

TLB refill 0x8000 0000

Cache

Error 0xA000

00100 (BNN: Why goes to 0xAxxxxx? A question to

readers. Please

think

about the difference between Kseg0 and kseg1)

All other exceptions 0x8000 0180

How MIPS acts when taking an exception?

1. It sets up the EPC to point to the restart location.

2. CPU changes into kernel mode and disables the interrupts (BNN: MIPS does this by

setting EXL bit of SR register)

3. Set up the Cause register to indicate which is wrong. So that software can tell the

reason for the exception. If it is for address exception, for example, TLB miss and so

on, the BadVaddr register is also set.

4. CPU starts

fetching instructions

from the exception

entry point and then goes to the

exception handler.

Returning from exceptions

Up to MIPS III, we use the eret instruciton to return to the original location before

falling

into

the

exception.

Note

that

eret

behavior

is:

clear

the

SR[EXL]

bit

and

returns

control to the adress stored in EPC.

An important bit in SR for interrupt handling

SR[IE]: This bit is used

to enable/disable interrupts,, including

the timer

interrupts.

Of couse,

when the SR[EXL] bit is set, this bit has no effects.

K0 and K1 registers:

These two registers are mostly used

by kernel

as a

temporary

buffer

to

hold some values

if necessary. So that you don't have to find some pre-defined

memories for that purpose.

One thing we

should be

careful

is : When you

are allowing

the nested exception/interrupt

handling, you need take care of these two registers' values as

they will be over-written, for example.

I

don't

encouarge

people

to

use

the

AT

register

too

often,

even

though

you

can

use

the

.set

noat directive. I have found a bug in mips-gcc, which will use the AT register anyway,

even

after we

use the .set

noat. In

other wrods, using AT is

dangeous somhow if you are

not quite familire with the register convention/usage

流水线

(Pipeline) and Interrupt Taken

我们知道，

MIPS

是一个

RISC

技术处理器。在某一个 时刻，在流水线上，同时有若干个指令被处

理在不同的阶段

(s tage)

上

.

MIPS

处理器一般采用

5

级 流水结构。

IF RD ALU MEM WB

那么我们要问：当一个

Interrupt

发生时，

CPU

到底该

如何

handle

？答案是这样的：

“

On an interrupt in a typical MIPS CPU, the last instruction to be completed before

interrupt

processing

starts

will

be

the

one

that

has

just

finished

its

MEM

stage

when

the

interrupt

is

detected.

The

exception

victim

will

be

the

one

that

has

just

finished

its

ALU

stage...

对上述的理解是这样的：

CPU

会< /p>

**

完成

**

那 条已

**finish**

MEM

stage

的指令。

然后将

excep tion

victim

定位在下一条

(following)

指令上。要注意的是：我们是在谈

In terrupt, not the

exception.

在

MIPS

中，这是有区别的。

下面介绍几个重要的

SR(Status Register)

与

Exception

和中断有关的位 。

* SR[EXL]

Exception Level; set by the processor when any exception other than Reset, So

ft Reset,

NMI, or Cache Error exception are taken. 0: normal 1: exception

When EXL is set:

-

Interrupts

are

disabled.

换句话说，

这时

SR[IE]

位是不管用了，

相当于所 有的中断都被

MASK

了。

- TLB refill exceptions

will use the

general exception vector

instead of the TLB refill

vector.

-

EPC

is

not

updated

if

another

exception

is

taken.

这一点要注意。如果我们想支持

nesting

exceptions,

我们要在

exception hander

中

clear EXL bit.

当然要先保存

EPC

的值。另外要注

< br>意的：

MIPS

当陷入

Exce ption/Interrupt

时，并不改变

SR[UX], SR[KX]

或

SR[SX]

的值。< /p>

SR[EXL]

为

1

自动的将

CPU mode

运行在

KERNEL

模式下。这一点要注意。

* SR[ERL]

Error Level; set

by the

processor

when Reset,

Soft Reset, NMI,

or

Cache Error exception

are taken. 0: normal 1: error

When ERL is set:

- Interrupts are disabled.

- The ERET instruction uses the return address held in ErrorEPC instead of EPC.

- Kuseg and xkuseg

are treated

as

unmapped

and uncached allows

main memory

to be accessed in the presence of cache errors.

这时刻，我们可以说，

MIPS CPU

只有在

这个时刻才是一种

**

实模式

(real mode)**.

* SR[IE]

Interrupt

Enable

0:

disable

interrupts

1:

enable

interrupts

。

请记住：

当

SR[EXL]