pimp在高边工作的MOSFET,其可能的失效模式和失效现象

Power MOSFET in High-Side Operating Modes, Possible Failure Modes, and Failure Signatures

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Power MOSFETs in high-side application can fail under any one of the following modes of operation:

(a) High-impedance gate drive

(b) Electro-static discharge (ESD) exposure

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(c) Electrical over- stressed (EOS) operation

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In most cases, failure analysis of the damaged MOSFET reveals a signature that can point towards a possible cause of failure.

(a) High-Impedance Gate Drive

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A generic schematic configuration for a high-side driver with inductive load is shown in figure 1. A typical gate drive design based on

an application-specific integrated circuit (ASIC) caters to the primary gate charge requirements of the MOSFET

, which are on the

order of a few tens to hundreds of nanocoulombs. An effort to achieve high efficiency and optimize the integration of the ASIC results

in low-

current (< 50 μA) gate drives (V2 referenced to power supply ground) with a high output impedance (> 1 M?). This basically

satisfies the total gate- charge requirements of the MOSFET

.

However

, to avoid overloading the ASIC, the external gate resistor (R2) in such a design tends to have a high ohmic value (ranging

from

tens

of

ohms

to

several

kiloohms).

The

feedback

resistor

(R3)

also

usually

has

a

high

ohmic

value

(ranging

from

several

kiloohms to 1 M?). As a result, the source (S) of the powe

r MOSFET (U1) is virtually floating.

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The effect is magnified during turn-off and recirculation of the energy stored in the inductor (L1).

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Fig. 1 - Typical High Side Driver

This

approach fully satisfies the requirements for steady-state operation, where small amount of current, on

the order of a few

microamps, is all that is required to maintain the on state. But it can be inadequate for dynamic (transient) turn-on and turn-off

operation of MOSFET

. In this latter case, the MOSFET switching operation can easily occur in linear mode, which is an unstable and

non-characterized area of MOSFET operation (figure 2).

Fig. 2 - Floating Source and Slow Turn- Off

During turn-on and turn-off, switching power losses are likely to dissipate from a very small area of the active die. The resulting failure

signature is high-power burn-out, with a random amount of damage located in the active area of the die. Invariably such failure is

labeled as EOS.

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Another subtle failure evidenced during the analysis of the failed MOSFET (with a virtually floating gate circuit configuration) is in the

gate- source area. A DC parameter test of the gate- source area shows out of spec readings. The failure mode is subtle insofar as the

leaky device recovers even during the DC parameter test. This failure mode remains under investigation to obtain a full explanation.

A failure example of a DPAK power MOSFET is shown in the figures 3, 4, and 5.

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Fig. 3 - EOS Damage Location

Fig. 4 - Damage on BPSG

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Fig. 5 - Damage on Gate Poly

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(b) Electro-Static Discharge (ESD) Exposures

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A second possible scenario arising from a virtually floating gate condition caused by the high impedance of an ASIC driver and/or high

gate resistor is increased susceptibility of the gate-source area for damage from ESD or a similar event. In addition to a typical ESD

event, high-energy, high- voltage transients of short duration can be generated from energy re-circulation and/or energy interruption

frominductive components. With reference to figure 6, these include the low- side load (L1, R1), other parallel connected load (L2, R4),

and series feed-in/harness impedance (L3, R5).

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Fig. 6 - L1, L2, L3 Sources of Transients

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Failure signatures are usually located near the gate termination and in the gate-source area. An example of a DPAK power MOSFET

failure is shown in figures 7, 8 and 9.

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Fig. 7 - ESD Damage near the Gate- Source

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Fig. 8 - ESD on the Gate Termination